Mark A Beiley, 581161 Dustin Ln, Chandler, AZ 85226

6362695, Mar 26, 2002

Dec 21, 1999

09/468478

Mark A. Beiley - Chandler AZ
James E. Breisch - Chandler AZ

Intel Corporation - Santa Clara CA

H03B 2900

331 78

A circuit includes a first oscillator having transistors to produce a first signal with random variations resulting from device channel resistance of the transistors.

6366320, Apr 2, 2002

Dec 8, 1997

08/987131

Rajendran Nair - Chandler AZ
Mark A. Beiley - Chandler AZ
Morteza Afghahi - Tempe AZ

Intel Corporation - Santa Clara CA

H04N 5335

348300, 348308

A semiconductor circuit having an analog storage array, a sense amplifier array in which each sense amp cell generates a differential signal pair in response to receiving first and second signals from the storage array. The circuit also includes an analog multiplexer through which a selected differential signal pair is driven into a signal processing pipe. In another embodiment, the sense amp cells each include an operational amplifier (opamp) pair configured as unity-gain closed loop amplifiers for driving the differential signal pair through the analog multiplexer. To improve settling time, the opamps are designed to provide an underdamped response while loaded with the analog transmission path through the analog mux. In yet another embodiment, each sense amp cell is activated one clock cycle before it is read. This allows speedy readout while transitioning from one cell to the next.

6410359, Jun 25, 2002

Mar 26, 2001

09/817639

Kevin M. Connolly - Chandler AZ
Jung S. Kang - Chandler AZ
Berni W. Landau - Beaverton OR
James E. Breisch - Chandler AZ
Akira Kakizawa - Phoenix AZ
Mark A. Beiley - Chandler AZ
Cory E. Weber - Beaverton OR
Shaofeng Yu - Lake Oswego OR

Intel Corporation - Santa Clara CA

H01L 2100

438 48

Leakage current may be reduced in trench isolated semiconductor devices by providing a buffer between the trench isolation and an active area. For example, with a trench isolated photodiode, a buffer of opposite conductivity type may be provided between the trench and the diffusion that forms the p-n junction of the photodiode.

6433822, Aug 13, 2002

Mar 31, 1998

09/052749

Lawrence T. Clark - Phoenix AZ
Mark A. Beiley - Chandler AZ
Eric J. Hoffman - Chandler AZ

Intel Corporation - Santa Clara CA

H04N 5217

348241, 348308

An architecture for self-calibration and fixed-pattern noise removal in imager chips. The column-to-column fixed pattern noise and/or pixel-to-pixel fixed pattern noise is determined through a self-calibration operation. During operation of the imager chip, when a value of a pixel is read, the read value is compensated with the fixed-pattern noise corresponding to either the column fixed pattern noise corresponding to the column having the pixel from which the value was read or to the pixel fixed pattern noise corresponding to the pixel from which the value was read.

6438276, Aug 20, 2002

Sep 11, 2000

09/659159

Jon M. Dhuse - Chandler AZ
Kevin M. Connolly - Chandler AZ
Mark A. Beiley - Chandler AZ

Intel Corporation - Santa Clara CA

G06K 920

382312

What is disclosed is an apparatus for reducing row reset noise in photodiode based complementary metal oxide (CMOS) sensors. The apparatus uses at least one reference pixel for each row of pixels in a sensor array. Also, a reset noise elimination unit is provided to adjust the values received from the pixels in a particular row by an adjustment value determined from the reset values received from the reference pixels. Additionally, a method of using the apparatus is disclosed. The method has a step of providing a first reset signal to a row of pixels including the reference pixels. The method also reads out a first set of values from this row after integration. The method continues with providing a second reset signal to the row and a second set of values is read from the row. An adjustment value is calculated from the difference of the values which are read out from the reference pixels.

6522357, Feb 18, 2003

Sep 30, 1997

08/939808

Mark A. Beiley - Chandler AZ
Eric J. Hoffman - Chandler AZ
Lawrence T. Clark - Phoenix AZ

Intel Corporation - Santa Clara CA

H04N 314

348296, 348308, 348310, 2502081

In a pixel having an electronic shutter, a method of increasing the retention time of the electronic shutter is disclosed. A reset signal is employed to drive a diode node to a predetermined voltage immediately after integration is completed. A sample signal is employed to control a pass gate. The sample signal includes a state where the sample signal is a negative voltage.

6806569, Oct 19, 2004

Sep 28, 2001

09/964811

James E. Breisch - Chandler AZ
Mark A. Beiley - Chandler AZ

Intel Corporation - Santa Clara CA

H01L 2334

257728, 257691, 257723, 257727

A mechanism is provided for delivering power to an on-die component (such as a buffer circuit). This may include a package unit having a low frequency delivery path and a high frequency delivery path and a die having the on-die component and a capacitive device each coupled in parallel between a first node and a second node. The die may further include a low frequency reception path and a high frequency reception path. The low frequency reception path may couple to the low frequency delivery path on the package unit and to the first node. The high frequency reception path may couple to the high frequency delivery path on the package unit and to the first node. The high frequency reception path may include a damping resistor.

6933168, Aug 23, 2005

Mar 9, 2001

09/802464

Edward J. Bawolek - Chandler AZ, US
Lawrence T. Clark - Phoenix AZ, US
Mark A. Beiley - Chandler AZ, US

Intel Corporation - Santa Clara CA

H01L021/00

438 70, 438 69, 257434, 257435, 257440

A method and apparatus for employing a light shield to modulate pixel color responsivity. The improved pixel includes a substrate having a photodiode with a light receiving area. A color filter array material of a first color is disposed above the substrate. The pixel has a first relative responsivity. A light shield is disposed above the substrate to modulate the pixel color responsivity. The light shield forms an aperture whose area is substantially equal to the light receiving area adjusted by a reduction factor. The reduction factor is the result of an arithmetic operation between the first relative responsivity and a second relative responsivity, associated with a second pixel of a second color.