Matthew D Dahl, 2920 Hawthorne St, Watertown, MA 02472

5850537, Dec 15, 1998

Feb 24, 1997

8/806542

Charles W. Selvidge - Charlestown MA
Anant Agarwal - Framingham MA
Johnathan Babb - Ringgold GA
Matthew L. Dahl - Marlboro MA

Virtual Machine Works, Inc. - Cambridge MA

G06F 9455

395500

A configurable logic system programmed to model a logic design comprises an array of programmable logic modules each configured to perform a partition block of the logic design and a module interconnect providing connections between the modules. The interconnect enables transmission of global links between the partition blocks of the modules. The modules time division multiplex the global links, with a destination module then demultiplexing the global links allowing the links to pass through to another FPGA. The modules are configured to transmit individual ones of the global links at time intervals determined in response to a ready time of the individual links. The ready times of individual global links are determined in response to receipt of parent global links and signal propagation delays across the modules. A parent of a particular global link is a link that affects a logic value of the global link. The present invention allows computation and communication simultaneously.

5649176, Jul 15, 1997

Aug 10, 1995

8/513605

Charles W. Selvidge - Charlestown MA
Matthew L. Dahl - Cambridge MA

Virtual Machine Works, Inc. - Cambridge MA

G06F 112

395551

A method of configuring a configurable logic system, including a single or multi-FPGA network, is disclosed in which an internal clock signal is defined that has a higher frequency than timing signals the system receives from the environment in which it is operating. The frequency can be at least ten times higher than a frequency of the environmental timing signals. The logic system is configured to have a controller that coordinates operation of its logic operation in response to the internal clock signal and environmental timing signals. Specifically, the controller is a finite state machine that provides control signals to sequential logic elements such as flip-flops. The logic elements are clocked by the internal clock signal. In the past, emulation or simulation devices, for example, operated in response to timing signals from the environment. A new internal clock signal, invisible to the environment, rather than the timing signals is used to control the internal operations of the devices.

5847578, Dec 8, 1998

Jan 8, 1997

8/780527

Michael Donald Noakes - Somerville MA
Charles W. Selvidge - Charlestown MA
Anant Argarwal - Framingham MA
Jonathan Babb - Ringgold GA
Matthew L. Dahl - Marlborough MA

Virtual Machine Works - Cambridge MA

H03K 738
H03K 1900

326 39

A programmable logic circuit includes a programmable logic array which generates a plurality of output signals for output from a single port on the programmable logic circuit, and which processes a plurality of input signals received from a single port on the programmable logic circuit. The programmable logic circuit also includes multiplexing means for receiving the plurality of output signals generated by the programmable logic array and for multiplexing the plurality of output signals. An output port outputs, from the programmable logic circuit, the multiplexed plurality of output signals generated by the programmable logic array. An input port receives a multiplexed plurality of input signals, and a demultiplexing means demultiplexes the multiplexed plurality of input signals and configurably communicates the demultiplexed plurality of input signals to the programmable logic array. This demultiplexing means and the multiplexing means are each operable at a clock speed which is different from a clock speed of the programmable logic array.

5659716, Aug 19, 1997

Nov 23, 1994

8/344723

Charles W. Selvidge - Charlestown MA
Anant Agarwal - Framingham MA
Johnathan Babb - Ringgold GA
Matthew L. Dahl - Marlboro MA

Virtual Machine Works, Inc. - Cambridge MA

G06F 9455

395500

A configurable logic system programmed to model a logic design comprises an array of programmable logic modules each configured to perform a partition block of the logic design and a module interconnect providing connections between the modules. The interconnect enables transmission of global links between the partition blocks of the modules. The modules time division multiplex the global links, with a destination module then demultiplexing the global links allowing the links to pass through to another FPGA. The modules are configured to transmit individual ones of the global links at time intervals determined in response to a ready time of the individual links. The ready times of individual global links are determined in response to receipt of parent global links and signal propagation delays across the modules. A parent of a particular global link is a link that affects a logic value of the global link. The present invention allows computation and communication simultaneously.

6009531, Dec 28, 1999

May 27, 1997

8/863963

Charles W. Selvidge - Charlestown MA
Matthew L. Dahl - Cambridge MA

Ikos Systems, Inc. - Cupertino CA

G06F 112

713400

A method of configuring a configurable logic system, including a single or multi-FPGA network, is disclosed in which an internal clock signal is defined that has a higher frequency than timing signals the system receives from the environment in which it is operating. The frequency can be at least ten times higher than a frequency of the environmental timing signals. The logic system is configured to have a controller that coordinates operation of its logic operation in response to the internal clock signal and environmental timing signals. Specifically, the controller is a finite state machine that provides control signals to sequential logic elements such as flip-flops. The logic elements are clocked by the internal clock signal. In the past, emulation or simulation devices, for example, operated in response to timing signals from the environment. A new internal clock signal, invisible to the environment, rather than the timing signals is used to control the internal operations of the devices.