Mauricio Serrano resumes & CV records
Resumes
Mauricio Serrano
Mauricio Garcia Serrano, 42Central Islip, NY
Mauricio Serrano Phones & Addresses
Central Islip, NY
Bay Shore, NY
College Point, NY
New York, NY
Mentions for Mauricio Garcia Serrano
Publications & IP owners
Us Patents
System For Target Branch Prediction Using Correlation Of Local Target Histories Including Update Inhibition For Inefficient Entries
US Patent:
7434037, Oct 7, 2008
Filed:
Apr 7, 2006
Appl. No.:
11/399979
Inventors:
Il Park - White Plains NY, US
Mauricio J. Serrano - Bronx NY, US
Mauricio J. Serrano - Bronx NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 9/32
US Classification:
712238
Abstract:
An information processing system includes a branch target buffer (BTB) comprising the last next address for the instruction and for receiving an indirect instruction address and providing a BTB predicted target; and next branch target table (NBTT) for storing potential branch targets based on a history of the branch and for providing an NBTT when the a BTB predicted target is not successful. In another embodiment a system comprising a plurality of branch prediction resources dynamically predicts the best resource appropriate for a branch. The method includes predicting a target branch for an indirect instruction address using a resource chosen among the plurality of branch prediction resources; and selectively inhibiting updates of the branch prediction resources whose prediction accuracy does not meet a threshold.
Mechanism For Data Cache Replacement Based On Region Policies
US Patent:
7793049, Sep 7, 2010
Filed:
Oct 30, 2007
Appl. No.:
11/929771
Inventors:
Harold W. Cain - Hartsdale NY, US
Jong-Deok Choi - Seongnam, KR
Pratak Pattnaik - Ossining NY, US
Mauricio J. Serrano - Bronx NY, US
Jong-Deok Choi - Seongnam, KR
Pratak Pattnaik - Ossining NY, US
Mauricio J. Serrano - Bronx NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 12/00
US Classification:
711133, 711145
Abstract:
A system and method for cache replacement includes: augmenting each cache block in a cache region with a region hint indicating a temporal priority of the cache block; receiving an indication that a cache miss has occurred; and selecting for eviction the cache block comprising the region hint indicating a low temporal priority.
Computer Implemented Method And System For Accurate, Efficient And Adaptive Calling Context Profiling
US Patent:
7818722, Oct 19, 2010
Filed:
Jun 9, 2006
Appl. No.:
11/450656
Inventors:
Mauricio Jose Serrano - Bronx NY, US
Xiaotong Zhuang - Quincy MA, US
Xiaotong Zhuang - Quincy MA, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 9/44
US Classification:
717130, 717127, 717128, 717131, 717133
Abstract:
Computer implemented method, system and computer usable program code for profiling the execution of an application that is both space- and time-efficient and highly accurate. A computer implemented method for profiling the execution of an application includes sampling execution characteristics of the application at a plurality of sampling points to provide samples, and deriving a calling context of the samples. The application is continuously executed between sampling points while additional profiling data is gathered.
Target Branch Prediction Using A Plurality Of Tables
US Patent:
7900026, Mar 1, 2011
Filed:
Oct 6, 2008
Appl. No.:
12/246282
Inventors:
Il Park - White Plains NY, US
Mauricio J. Serrano - Bronx NY, US
Mauricio J. Serrano - Bronx NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 9/32
US Classification:
712239, 712240
Abstract:
A system for predicting multiple targets for a single branch includes: a branch target buffer that includes a previous next address for an instruction and that receives an indirect instruction address to provide a first branch target prediction; a first branch table for capturing local past target information of an indirect branch in an encoded form; a second branch table which is a correlation table for storing potential branch targets based on a local branch history and which provides a second branch target prediction when the first branch target prediction is not successful; an exclusion predictor for inhibiting updates of inefficient entries; and a multiplexer to select the predicted target as output.
Preferred Write-Mostly Data Cache Replacement Policies
US Patent:
7921260, Apr 5, 2011
Filed:
Oct 24, 2007
Appl. No.:
11/923625
Inventors:
Jong-Deok Choi - Seongnam, KR
Mauricio J. Serrano - Bronx NY, US
Mauricio J. Serrano - Bronx NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 12/12
US Classification:
711133
Abstract:
A computer-implemented method of cache replacement includes steps of: determining whether each cache block in a cache memory is a read or a write block; augmenting metadata associated with each cache block with an indicator of the type of access; receiving an access request resulting in a cache miss, the cache miss indicating that a cache block will need to be replaced; examining the indicator in the metadata of each cache block for determining a probability that said cache block will be replaced; and selecting for replacement the cache block with the highest probability of replacement.
Computer Implemented Method And System For Accurate, Efficient And Adaptive Calling Context Profiling
US Patent:
8122438, Feb 21, 2012
Filed:
Jun 18, 2008
Appl. No.:
12/141222
Inventors:
Mauricio Jose Serrano - Bronx NY, US
Xiaotong Zhuang - Quincy MA, US
Xiaotong Zhuang - Quincy MA, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 9/44
US Classification:
717130, 717127, 717128, 717131, 717133
Abstract:
Computer implemented method, system and computer usable program code for profiling the execution of an application that is both space- and time-efficient and highly accurate. A computer implemented method for profiling the execution of an application includes sampling execution characteristics of the application at a plurality of sampling points to provide samples, and deriving a calling context of the samples. The application is continuously executed between sampling points while additional profiling data is gathered.
Data Placement Optimization Using Data Context Collected During Garbage Collection
US Patent:
8621150, Dec 31, 2013
Filed:
Apr 9, 2010
Appl. No.:
12/757173
Inventors:
Mauricio J. Serrano - Bronx NY, US
Xiaotong Zhuang - White Plains NY, US
Xiaotong Zhuang - White Plains NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 12/00
G06F 13/00
G06F 13/28
G06F 13/00
G06F 13/28
US Classification:
711118, 711166, 711E12009, 711E12017
Abstract:
Mechanisms are provided for data placement optimization during runtime of a computer program. The mechanisms detect cache misses in a cache of the data processing system and collect cache miss information for objects of the computer program. Data context information is generated for an object in an object access sequence of the computer program. The data context information identifies one or more additional objects accessed as part of the object access sequence in association with the object. The cache miss information is correlated with the data context information of the object. Data placement optimization is performed on the object, in the object access sequence, with which the cache miss information is associated. The data placement optimization places connected objects in the object access sequence in close proximity to each other in a memory structure of the data processing system.
Redundant Transactional Memory
US Patent:
2013001, Jan 17, 2013
Filed:
Jul 11, 2011
Appl. No.:
13/179672
Inventors:
David M. Daly - Croton on Hudson NY, US
Kattamuri Ekanadham - Mohegan Lake NY, US
Michael C. Huang - Rochester NY, US
Jose E. Moreira - Irvington NY, US
Mauricio J. Serrano - Bronx NY, US
Kattamuri Ekanadham - Mohegan Lake NY, US
Michael C. Huang - Rochester NY, US
Jose E. Moreira - Irvington NY, US
Mauricio J. Serrano - Bronx NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 9/30
US Classification:
712203, 712E09016
Abstract:
A mechanism is provided for redundant execution of a set of instructions. A redundant execution begin (rbegin) instruction to be executed by a first hardware thread on the first processor is identified in the set of instructions. The set of instructions immediately after the rbegin instruction are executed on the first hardware thread and on a second hardware thread. Responsive to both the first processor and the second processor ending execution of the set of instructions, responsive to a first set of cache lines in a first speculative store matching a second set of cache lines in a second speculative store, and responsive to a first set of register states in a first status register matching a second set of register states in a second status register, dirty lines in the first speculative store are committed thereby committing a redundant transaction state to an architectural state.
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