Maximino S VasquezAnaheim, CA
Maximino Vasquez Phones & Addresses
Anaheim, CA
San Jose, CA
2775 Rainview Dr, San Jose, CA 95133 408-5699018
Work
Position:
Precision Production Occupations
Education
Degree:
Bachelor's degree or higher
Mentions for Maximino S Vasquez
Publications & IP owners
Us Patents
Combined Vertical Filter For Graphic Displays
US Patent:
6563544, May 13, 2003
Filed:
Sep 10, 1999
Appl. No.:
09/393480
Inventors:
Maximino Vasquez - Fremont CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H04N 1120
US Classification:
348447, 348446, 348607, 348910
Abstract:
An apparatus and method for converting computer graphics images into a format suitable for display on a TV. A flicker filter is combined with a vertical scaling filter and/or vertical overscan compensation filter to produce an interlaced image formatted for display on a TV, more efficiently than if the processes occurred sequentially. The apparatus and method are not limited to any particular filter sizes or set of filter coefficient values. The apparatus and method may be used as part of a multimedia computer system.
Block-Oriented Pixel Filter
US Patent:
6711301, Mar 23, 2004
Filed:
Jan 31, 2000
Appl. No.:
09/494745
Inventors:
David Huu Tran - Los Altos CA
Maximino Vasquez - Fremont CA
Daniel Robert Joe - San Jose CA
Maximino Vasquez - Fremont CA
Daniel Robert Joe - San Jose CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06K 940
US Classification:
382260, 382261, 382298, 708313
Abstract:
A method and apparatus for block-oriented pixel filtering reduces the number of hardware multipliers required for an image processing operation by increasing the speed of the pixel filter and rearranging the math operations. A sorter is employed in the line buffers so that defined groups of input pixel components are provided to the multipliers of the pixel filter. An accumulator is employed to receive products from the multipliers and assemble output pixels. The savings in gate count from reducing the number of multipliers is greater than additional costs, if any, of the sorter and other logic. The method and apparatus of the invention also simplify the addressing logic for the provision of scaling coefficients during an image processing operation.
Dvd Subpicture Rendering Without Loss Of Color Resolution
US Patent:
6912350, Jun 28, 2005
Filed:
Dec 8, 1999
Appl. No.:
09/458109
Inventors:
Maximino Vasquez - Fremont CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H04N005/91
US Classification:
386 95, 386125, 386126
Abstract:
A method an apparatus for rendering DVD subpicture data on a computer system having graphics data without a loss of subpicture resolution includes inserting a key into the subpicture data during or right after decoding and storing the subpicture data in the primary graphics surface. This key indicates whether the data is graphics (GUI) information or subpicture information. The key is then examined by hardware logic in the graphics chip, allowing other hardware logic to blend DVD subpicture data with DVD video data without losing subpicture color resolution. The key may be implemented differently for different color modes of the primary surface, and may be unnecessary in certain modes.
Viterbi Decoder And Method Using Sequential Two-Way Add-Compare-Select Operations
US Patent:
7020223, Mar 28, 2006
Filed:
Apr 16, 2002
Appl. No.:
10/123744
Inventors:
Maximino Vasquez - Fremont CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H04L 27/06
H03M 13/03
H03M 13/03
US Classification:
375341, 714795, 714796
Abstract:
In a Viterbi decoder, 2-way add-compare-select (ACS) operations are performed by sequential and/or parallel two-way ACS operations. In one embodiment, first two-way ACS operations generate an interim path metric for each of a plurality of interim states. Second two-way ACS operations generate a path metric for each of a plurality of next states. This process may be repeating for subsequent groups of bits to generate branch transitions through a trellis. A path having a lowest path metric may be selected and a decoded bit sequence determined based on the selected path. In generating the decoded bit sequence, the interim states of the selected path do not have to be used for code rates k/n when k is two or greater. The interim states may be used for code rates k/n when k=1.
Viterbi Decoder And Decoding Method Using Rescaled Branch Metrics In Add-Compare-Select Operations
US Patent:
7046747, May 16, 2006
Filed:
Apr 16, 2002
Appl. No.:
10/123764
Inventors:
Maximino Vasquez - Fremont CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03D 1/00
H03M 13/03
H03M 13/03
US Classification:
375341, 714795, 714796
Abstract:
A Viterbi decoder and method rescale branch metrics by a minimum value of a prior state's path metric. A branch metric unit generates branch metrics from groups of bits of a received bit stream, and an ACS operation unit rescales the branch metrics and performs ACS operations to generate path metrics for the next state of the decoder. The rescaled branch metrics may be stored in branch metric registers of the ACS operation unit for use in a subsequent ACS operation. Rather than rescaling path metrics within individual ACS elements, branch metric rescaling is performed outside the individual ACS elements.
Method And Apparatus For Varied Format Encoding And Decoding Of Pixel Data
US Patent:
7627182, Dec 1, 2009
Filed:
Dec 30, 2005
Appl. No.:
11/323930
Inventors:
Maximino Vasquez - Fremont CA, US
Pierre Selwan - Fremont CA, US
Pierre Selwan - Fremont CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06K 9/36
H04N 7/12
G06K 9/46
H04N 7/12
G06K 9/46
US Classification:
382232, 37524008
Abstract:
An apparatus, system, and method for encoding video pixels is provided in some embodiments. At least one encoder may encode a video pixel data as a symbol. A selection unit may select the symbol. A selection of the symbol is a function of a pixel format that is of one of a plurality of pixel formats employable the apparatus, system or method.
Graphics Controller, Display Controller And Method For Compensating For Low Response Time In Displays
US Patent:
7876313, Jan 25, 2011
Filed:
Sep 29, 2006
Appl. No.:
11/536904
Inventors:
Pierre Selwan - Fremont CA, US
Maximino Vasquez - Fremont CA, US
Maximino Vasquez - Fremont CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G09G 5/00
US Classification:
345204, 345501
Abstract:
Embodiments of a graphics controller, display controller and method for compensating for low-response-time (LRT) displays are generally described herein. Other embodiments may be described and claimed. In some embodiments, an interleaved pixel stream is provided by a graphics controller to a display controller. The display controller may select low-response-time compensation for each pixel of the current frame based on the pixels of the current frame and corresponding pixels of the prior frame without the use of a frame buffer on a display panel.
Protocol Extensions In A Display Port Compatible Interface
US Patent:
7961656, Jun 14, 2011
Filed:
Sep 29, 2008
Appl. No.:
12/286192
Inventors:
Seh Kwa - Saratoga CA, US
Maximino Vasquez - Fremont CA, US
Jim Kardach - Saratoga CA, US
Maximino Vasquez - Fremont CA, US
Jim Kardach - Saratoga CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H04L 12/56
H04J 1/16
H04J 1/16
US Classification:
370282, 370252, 370278, 370419
Abstract:
Contents of extension packets of a DisplayPort specification are described that can permit a computer to control a target device. In one example, an extension packet controls the target device in at least one of power consumption, image rendering, and register updating.
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