Micah R Mcdaniel, 514317 Myrtle Beach Dr, Austin, TX 78738

7587444, Sep 8, 2009

Apr 26, 2005

11/114238

Micah Rone McDaniel - Austin TX, US
Ann Sekli Chin - Austin TX, US
Daniel Kershaw - Cambridge, GB

ARM Limited - Cambridge

G06F 7/50

708709, 708714

A data processing apparatus for summing data values includes: a plurality of adder logic stages arranged in parallel; a control logic, in response to a request to sum two data values, to forward portions of the two data values to respective ones of the plurality of adder logic stages, each of the plurality of adder logic stages performing a carry propagate addition of the received portions to generate an intermediate sum, a propagate value and a carry; and further logic stages for combining the intermediate sums, carries and propagate values to produce a sum of the two data values. The control logic, further in response to a request to add a third data value to the sum before the further logic has completed sum, forwards portions of the third data value to respective ones of the plurality of adder logic stages, feedbacks the intermediate sums, and selectively feedbacks a carry generated from a preceding adder logic stage. The plurality of adder logic stages perform a carry propagate addition of the fedback intermediate sums and carrys with respective portions of the third data value to generate a plurality of further intermediate sums, further carrys and further propagate values. The further logic stages combine the further intermediate sums, carries and propagate values to produce a sum of the three data values.

2003002, Feb 6, 2003

Aug 3, 2001

09/922516

Robert McDonald - Austin TX, US
Barry Williamson - Cedar Park TX, US
Micah McDaniel - Austin TX, US

G06F015/00

712/034000

An acceleration engine may include a set of accelerators and a set of resources coupled to the accelerators. The resources may interface the accelerators to an interconnect, and may provide a programming interface to the accelerators. Since the resources handle interfacing the accelerators to a given interconnect, the accelerators may be insulated from the details of a given system. If more than one accelerator is included in the acceleration engine, some of the resources may be shared by the accelerators. For example, if the resources include a memory for storing data accessed by an accelerator, the memory may be shared between by the accelerators. A methodology for creating an acceleration engine is also described.

2005021, Sep 22, 2005

Mar 19, 2004

10/804181

Daniel Kershaw - Austin TX, US
Micah McDaniel - Austin TX, US

ARM LIMITED - Cambridge

G06F007/00

708209000

A saturating shifter is provided which operates to detect in parallel with a shifting operation whether the result of that shifting operation will require saturating. If saturation is required, then the necessary saturating mask may be determined earlier and accordingly processing speed increased.

2005027, Dec 8, 2005

Jun 3, 2004

10/859597

Daniel Kershaw - Austin TX, US
Micah McDaniel - Austin TX, US

ARM LIMITED - Cambridge

G06F007/52

708700000

A method and apparatus for generating a plurality of concurrent significant bits forming at least a portion of a product from at least two partial products, the method comprising the following steps: for each of a plurality of said concurrent predetermined significant bits performing steps (i) to (iii): (i) performing an addition of bits of a predetermined significance from each of said plurality of partial products having a bit of said predetermined significance; (ii) forming an intermediate sum of said predetermined significance from the least significant bit of said additions; (iii) forming at least one intermediate carry of a higher significance from said higher significant bits of said sum; and detecting if said partial products are formed from integers or polynomials; and outputting said plurality of intermediate sum bits formed during steps (i) to (iii) as a plurality of product bits of corresponding significance in response to detection of polynomials; or combining said intermediate carrys and said intermediate sum bits with a same significance to produce a product bit of a corresponding significance in response to detection of integers, and outputting said combination as a plurality of product bits of corresponding significance.