Michael P Lamacchia, 68510 Spur St, Gilbert, AZ 85296

2008007, Mar 20, 2008

Aug 29, 2006

11/512561

Michael Philip LaMacchia - Gilbert AZ, US
Byron Tarver - Chandler AZ, US
Bill Haber - Tempe AZ, US
Dale Schiele - Scottsdale AZ, US

G06F 12/14

713193

A secure virtual RAM securely transfers data within a device having a secure, non-volatile memory and a host. The secure virtual RAM includes a memory management component configured to direct the transfer of the data between the non-volatile memory and a processor, and an encryption/decryption component coupled to the memory management component and configured to decrypt the data provided to the processor and encrypt the data provided to the non-volatile memory. The secure virtual RAM further includes an integrity check component coupled to the encryption/decryption component and configured to monitor functional integrity, a key storage component coupled to the encryption/decryption component and configured to receive cryptographic keys and provide the cryptographic keys to the encryption/decryption component.

5930359, Jul 27, 1999

Sep 23, 1996

8/717557

Robert Alan Kempke - Tempe AZ
Anthony J. McAuley - Bloomfield NJ
Michael P. Lamacchia - Gilbert AZ

Motorola, Inc. - Schaumburg IL

H04K 102
H04K 112
H04L 900
H04L 112
G11C 1500

380 9

A system for a pipeline cascaded content addressable memory CAM system for sequentially processing input data includes an input register, a CAM core, cascade logic and an output register. As the memory association functions produce matches in the CAM core, the cascade logic in parallel composites data associated with each matching CAM core. Each cascade processes a separate data input simultaneously then passes on the cumulative results to the next stage.

6108419, Aug 22, 2000

Jan 27, 1998

9/013550

Michael Philip LaMacchia - Gilbert AZ
Bobby Glen Barker - Gilbert AZ
Chuckwudi Perry - Scottsdale AZ

Motorola, Inc. - Schaumburg IL

H04K 100

380 2

A method of evaluating a cryptosystem to determine whether the cryptosystem can withstand a fault analysis attack, the method includes the steps of providing a cryptosystem having an encrypting process to encrypt a plaintext into a ciphertext, introducing a fault into the encrypting process to generate a ciphertext with faults, and comparing the ciphertext with the ciphertext with faults in an attempt to recover a key of the cryptosystem.

4623846, Nov 18, 1986

Feb 14, 1985

6/701727

Michael P. LaMacchia - Chandler AZ

Motorola, Inc. - Schaumburg IL

H03K 301

328 61

A digital clock generator circuit which accepts a rate signal and a master clock signal and generates an output clock signal exhibiting a frequency which is programmed by the rate signal is disclosed. A constant duty cycle characteristic of the output clock signal is obtained regardless of the output clock signal's frequency. A memory element which generates the output signal is placed in one logical state when a counter portion of the present invention reaches a terminal count. The memory element is placed in an opposing logical state whenever the counter achieves 1/2 of its programmed value. A duty cycle compensator makes small timing adjustments to compensate for any truncation error which occurs in dividing the rate signal by two.

5937285, Aug 10, 1999

May 23, 1997

8/863109

Jonathan K. Abrokwah - Tempe AZ
Ravi Droopad - Tempe AZ
Corey D. Overgaard - Phoenix AZ
Brian Bowers - Mesa AZ
Michael P. LaMacchia - Gilbert AZ
Bruce A. Bernhardt - Chandler AZ

Motorola, Inc. - Schaumburg IL

H01L 2120

438172

A method of fabricating submicron HFETs includes forming a buffered substrate structure with a supporting substrate of GaAs, a portion of low temperature AlGaAs grown on the supporting substrate at a temperature of approximately 300. degree. C. , a layer of low temperature GaAs grown on the portion AlGaAs layer at a temperature of 200. degree. C. , a layer of low temperature AlGaAs grown on the GaAs layer at a temperature of 400. degree. C. , and a buffer layer of undoped GaAs grown on the second AlGaAs layer. Complementary pairs of HFETs can be formed on the buffered substrate structure, since the structure supports the operation of p and n type transistors equally well.

5600260, Feb 4, 1997

Jun 29, 1995

8/496651

Michael P. LaMacchia - Gilbert AZ
William O. Mathes - Tempe AZ

Motorola, Inc. - Schaumburg IL

H03K 19003
H03K 1900

326 11

A method and apparatus for hardening current steering logic (CSL) to soft errors (charged particles passing through and upsetting the logic state of an integrated circuit) includes a hardened CSL circuit or cell (20), including three or more circuit cell elements (21) in parallel. The circuit cell elements (21) redundantly perform a single cell function. Each of the circuit cell elements (21) is coupled to soft error immune resistive elements (24 and 25) within a summing element (22). Current (23) is steered through the resistive elements (24 and 25) depending upon input signals (26) to each of the circuit cell elements (21). The logical output signal (27) is unaffected by a single soft error event since the majority of the total current (23) remains steered through the correct resistive element (24 or 25).

5949248, Sep 7, 1999

Oct 2, 1997

8/943021

Michael Philip LaMacchia - Gilbert AZ
William Oliver Mathes - Tempe AZ
Bruce Alan Fette - Mesa AZ

Motorola Inc. - Schaumburg IL

H03K 19003
H03K 1716

326 9

A single event upset (SEU) sensitivity control system (42) dynamically hardens a digital circuit (48) to single event upsets. The sensitivity control system (42) includes an upset rate sensor (66) for detecting a quantity of particles (38) that cause single event upsets. A noise margin control circuit (70) is configured to adjust a noise margin (46) of the digital circuit (48) in response to the quantity of particles (38). Noise margin (46) is increased when a particle density (34) is high to decrease the sensitivity of the digital circuit (48) to single event upsets. Additionally, noise margin (46) is decreased when a particle density (36) is low to decrease the power consumption level of digital circuit (48).