Michael J Lundberg, 34New York, NY

6704302, Mar 9, 2004

Feb 4, 1999

09/245137

Saul Joseph Einbinder - Monmouth NJ
Michael Robert Lundberg - Monmouth NJ
Scott A. Magnuson - Monmouth NJ

Avaya Technology Corp. - Basking Ridge NJ

H04L 12413

370352, 370389, 370447, 370461, 370463

A port prioritizing device that interfaces a computer device and a telecommunications terminal device with a data network that is normally used exclusively for carrying data associated with computer devices. The port prioritizing device accepts packetized data from the computer and the telecommunications devices, merges that data and sends it out to the data network. The port prioritizing device provides a higher priority for data packets from the telecommunications device, by blocking the transmission of computer data packets while telecommunications data packets are being sent.

7583792, Sep 1, 2009

Jul 7, 2005

11/176816

William Howard Chriss - Holmdel NJ, US
Michael Robert Lundberg - Holmdel NJ, US
Shashank Sarwate - Ocean NJ, US
Diane Somers - Holmdel NJ, US
M. Umit Uyar - Holmdel NJ, US

Avaya Inc. - Basking Ridge NJ

H04M 1/24
H04M 3/08
H04M 3/22

379 1002, 379 101, 379 1501, 379 2704

A method and apparatus are disclosed that provide a technique for testing a data-processing system that enables communications between two or more telecommunications endpoints. An example of such a data-processing system is a Session-Initiation Protocol (SIP) proxy server. In particular, a test-execution system, in accordance with the illustrative embodiment of the present invention, transmits test-related signals to and receives test-related signals from one or more endpoints, such as SIP-enabled telephones. Some of the transmitted test-related signals direct an endpoint to transmit a message, such as a session-initiation request, to the data-processing system under test. Some of the received test-related signals comprise information from an endpoint, such as whether or not a message has been received from the data-processing system under test. Instead of communicating with the data-processing system itself, the test-execution system of the illustrative embodiment enlists the telecommunications endpoints to interact with the data-processing system.

8059788, Nov 15, 2011

Jun 27, 2007

11/769472

Muharrem Umit Uyar - Holmdel NJ, US
Michael Robert Lundberg - Holmdel NJ, US
Diane Somers - Holmdel NJ, US
Shashank Sarwate - Ocean NJ, US
William Howard Chriss - Holmdel NJ, US

Avaya Inc. - Basking Ridge NJ

H04M 1/24

379 2701, 379 2704

The present invention provides a system and method for a computer controlled test system in which the computer can change and monitor the compound observable state of an electronic device or telephone during testing procedure. In the preferred embodiment of the invention, the compound observable state of the electronic device includes a display bit map file or the status of lights or buttons. The compound observable state can be evaluated by the computer in real-time to alert nearby operators of a failure (i. e. a telephone that needs to be rebooted) or malfunction (not rising to the level of a failure). Also, the data related to the compound observable state can be stored in the computer for later review to assist in debugging the telephone's software.

4604500, Aug 5, 1986

Dec 2, 1981

6/326908

Sanford S. Brown - River Plaza NJ
Dennis J. Hunsberger - Lincroft NJ
Michael R. Lundberg - Bridgewater NJ

AT&T Bell Laboratories - Murray Hill NJ

G06F 900

179 18ES

There is disclosed an interrupt arrangement for use in a multiprocessing system where it is desired to specifically direct interrupts from one processor to any other processor. The arrangement treats the interrupt signal as a data communication between processors. In this regard, common address space is set aside, on a system basis, for interrupt signals. A sending processor first contends for the system bus and then addresses a message to a specific target processor. The message is received at the target processor over the regular communication channel and stored in a FIFO memory. Interrupt messages filter through the memory in order of arrival and cause interrupts to occur at the target processor. The information at the output of the FIFO memory controls the processing of the interrupt.

5896512, Apr 20, 1999

Sep 11, 1996

8/712009

Saul Joseph Einbinder - Holmdel NJ
Michael Robert Lundberg - Middletown NJ
Charles Timothy Martin - Aberdeen NJ
Stephen George Pisano - Middletown NJ

Lucent Technologies Inc. - Murray Hill NJ

G06F 1700
G06F 1300

3952008

An interface unit for interfacing a computer device and a telecommunications terminal device such, for example, as a telephone, with a data network capable of carrying data associated with each type of device. The interface unit is powered independently from the computer device and includes both the processing and memory resources needed to interact with the network and an interface for establishing a link to the telecommunications terminal.