Michael F MaasWoodbury, MN

7016430, Mar 21, 2006

Mar 21, 2001

09/814194

Edward L. Grivna - Brooklyn Park MN, US
Michael F. Maas - Mendota Heights MN, US

Cyrpess Semiconductor Corp. - San Jose CA

H04B 15/00

375285, 370252, 714752, 714758, 714746, 714786

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a first select signal, a second select signal and a first data stream in response to an input data stream and an exception signal. The second circuit may be configured to generate an output data stream in response to the first data stream, the first select signal and the second select signal. The second circuit may be configured to replace one or more characters of the first data stream.

7532645, May 12, 2009

Jan 14, 2005

11/035613

Khaldoun Bataineh - Austin TX, US
Stephen D. Anderson - Minnetonka MN, US
Michael Maas - Mendota Heights MN, US
David E. Tetzlaff - Minnetonka MN, US

Xilinx, Inc. - San Jose CA

H04J 3/07

370503, 370509, 375316, 375355, 375376, 375374, 375375

A receiver that includes: an oversampling module that converts a serial stream of data into a plurality of streams of oversampled data based on the receive clock; a transition location module that determines transition locations of the streams of oversampled data and the receive clock; a pointer adjust module that determines a pointer variable based on the transition locations and the receive clock; a data selection module that determines an equivalent data value for the streams of oversampled data based on the pointer variable; a staging register module that produces an offset data word and an extra data word from the equivalent data value for the oversampled data streams; and a output register module that produces a parallel data output from at least one of the offset data word and the extra data word.

4912709, Mar 27, 1990

Oct 23, 1987

7/112920

Judy L. Teske - Burnsville MN
Daniel J. Baxter - St. Paul MN
Don A. Daane - Burnsville MN
Brian D. Borchers - Burnsville MN
David H. Allen - Eagan MN
Michael F. Maas - Maplewood MN

Control Data Corporation - Minneapolis MN

G01R 3128

371 221

This application describes a peripheral cell structure for VLSI chips that requires the use of standard cells having both input and output capability connected to nearly all of the signal carrying pins. The cells function is alterable (to input or output and to where the data input signals originate) by control signals which may originate with a control register. The clock input signal is split into two independent signals to selectively disable the input or output registers, thus allowing the control register to be changed without affecting the contents of the other two registers. An early signal is also provided to prepare for mode changes.

4486715, Dec 4, 1984

Aug 4, 1982

6/404955

Michael F. Maas - White Bear Lake MN
Max S. Hendrickson - Forest Lake MN

Honeywell Inc. - Minneapolis MN

H03D 1300
H04L 2714
H03K 906

329 50

A frequency shift key demodulator produces an output data stream based upon whether a FSK modulated input signal has a frequency (f. sub. FSK) which is greater than or less than a reference frequency (f. sub. 0) of a reference (REF) signal. The demodulator includes a sequence generator which generates a two bit binary code which represents the phase angle between the FSK and REF signals. The sequence of the code indicates the sign of the phase velocity between the FSK and REF signals. The demodulator also includes first and second sequence detectors, first and second integrating shift registers, and a decision circuit. The first sequence detector provides an output signal to the first shift register indicating that the FSK signal has a frequency less than the REF signal based upon detection of a first predetermined sequence of the code from the sequence generator. Similarly, the second sequence detector senses a second predetermined sequence of the code indicating that the FSK signal has a frequency greater than the REF signal and provides an output signal to the second shift register. At the end of a predetermined time period, the decision circuit compares the content of the first and second shift registers and produces an output bit of the data stream.

4771251, Sep 13, 1988

Oct 23, 1987

7/112915

David H. Allen - Eagan MN
Michael F. Maas - Maplewood MN

Control Data Corporation - Minneapolis MN

H03B 2800
G01R 1512

331 57

An improved ring oscillator for VLSI chips is shown, formed at the chip periphery. It may have specific initiation gates and have additional parasitic capacitance added to the ring to enhance accuracy. The circuit elements used for the ring are the same as those used for more centralized circuits.

4499425, Feb 12, 1985

Aug 4, 1982

6/404959

Michael F. Maas - White Bear Lake MN

Honeywell Inc. - Minneapolis MN

H03D 1300
H03K 906
H04L 2714

329 50

A frequency shift key receiver includes a phase velocity sign detector which detects whether a FSK modulated input signal has a frequency (f. sub. FSK) which is greater than or less than a reference frequency (f. sub. 0) of a REF signal. The phase velocity sign detector includes a sequence generator which generates a two bit binary code which represents the phase angle between the FSK and REF signals. The sequence of the code indicates the sign of the phase velocity between the FSK and REF signals. The phase velocity sign detector includes a sequence detector which provides an output signal indicating whether the FSK signal has a frequency greater than or less than the REF signal based upon the sequence of the code from the sequence generator. The phase velocity sign detector demodulates the FSK signal in the digital domain using circuitry which is completely integrable on a monolithic integrated circuit chip.