Michael A MayerChicago, IL

2011022, Sep 15, 2011

Mar 11, 2010

12/721756

Michael J. Tortorello - Oak Lawn IL, US
Michael A. Mayer - Chicago IL, US

Elkay Manufacturing Company - Oak Brook IL

F16K 31/44
F16K 51/00

251231, 137 1518

A faucet handle connector that securely attaches a grip of a faucet handle to a valve apparatus for regulating the flow rate and/or temperature of water through a faucet spout. The faucet handle connector provides a structure for convenient attachment of the faucet handle to the valve apparatus. In addition, the faucet handle connector attaches the faucet handle to the valve apparatus in a manner that conceals the faucet handle connector from a user to improve the aesthetic characteristics of the faucet and to reduce the number of parts required for assembly. Thus, the faucet handle connector attaches the faucet handle to the valve apparatus without the use of a screw or any other observable fastener, and a separate cover or similar structure is not required to hide the connector.

4989210, Jan 29, 1991

Mar 19, 1990

7/499231

James H. Scheuneman - St. Paul MN
Paul L. Peirson - Forest Lake MN
Michael E. Mayer - Fridley MN

Unisys Corporation - Blue Bell PA

G06F 1110

371 401

A memory system which is shared by a plurality of requestors each of which supply read and write address bits to the memory system is read out of, or written into, in accordance with read and write address bits. A sequencer is utilized to initiate a sequence of timing signals that control the reading, writing and partial writing of data. Certain ones of these signals occur at fixed intervals from the receipt of an initial load address signal. A read address circuit coupled to receive the read address bits generates a set of check bits. A read address stack means stores each set of read address check bits upon the occurrence of an associated load read address stack signal. A write address check bit generator means is coupled to receive write address bits and to generate a set of check bits representative of the write address bits. A write address stack means stores each set of the write address check bits upon the occurrence of an associated load write address stack signal. A read address stack selector and a write address stack selector read out read address check bits and write address check bits, while the sequencer controls the transmission of the read address check bits and the write address check bits to an error detection circuit.

2018031, Nov 1, 2018

Dec 1, 2017

15/828680

- Deerfield IL, US
- Tokyo, JP
Himanshu Naik - Evanston IL, US
Michael Mayer - Antioch IL, US
Kanji Komatsu - Tokyo, JP

Takeda Pharmaceuticals U.S.A., Inc. - Deerfield IL
Teijin Pharma Limied - Tokyo

A61K 31/426
A61K 9/50
A61K 31/165
A61K 9/16

Methods and pharmaceutical compositions for reducing number of gout flares experienced by a patient are disclosed. The methods can comprise administering to a patient with hyperuricemia an effective amount of a xanthine oxidase inhibitor in a modified release dosage form once daily or in an immediate release dosage form two or more times daily to prevent at least one gout flare or reduce the number of gout flares experienced by the patient.

2014035, Dec 4, 2014

May 30, 2014

14/292010

- Deerfield IL, US
- Tokyo, JP
Himanshu Naik - Evanston IL, US
Michael Mayer - Antioch IL, US
Kanji Komatsu - Tokyo, JP

A61K 31/426
A61K 31/165

514365

Methods and pharmaceutical compositions for reducing number of gout flares experienced by a patient are disclosed. The methods can comprise administering to a patient with hyperuricemia an effective amount of a xanthine oxidase inhibitor in a modified release dosage form once daily or in an immediate release dosage form two or more times daily to prevent at least one gout flare or reduce the number of gout flares experienced by the patient.