Michael C Panis, 571088 Broadway, Somerville, MA 02144

6550036, Apr 15, 2003

Oct 1, 1999

09/409618

Michael C. Panis - Brookline MA

Teradyne, Inc. - Boston MA

G06F 1100

714815, 714744, 714814, 324 7644, 324 7659, 324 7662, 368113

A pre-conditioner for enabling high-speed time interval measurements in an ATE system having a relatively low-bandwidth pathway between a UUT and a timer/counter includes a frequency divider and a D flip-flop located near the UUT. The frequency divider receives a first input signal from the UUT and produces a first output signal having a frequency equal to 1/N times the frequency of the first input signal. The first output signal connects over the low-bandwidth pathway to a first channel of the timer/counter. The first output signal also connects to the D input of the D flip-flop. The pre-conditioner receives a second input signal from the UUT that drives the CLOCK input of the D flip-flop. The Q output of the D flip-flop supplies a second output of the pre-conditioner. The second output connects over the low-bandwidth pathway to a second channel of the timer/counter.

6981192, Dec 27, 2005

Sep 27, 2002

10/256586

Michael C. Panis - Brookline MA, US

Teradyne, Inc. - Boston MA

G11B020/20
G06F011/00

714740, 714700

A pin electronics circuit for automatic test equipment includes first and second sampling circuits for sampling first and second legs of a differential signal produced by a DUT (Device Under Test). Timing signals activate the first and second sampling circuits to sample the legs of the differential signal at precisely defined instants of time to produce first and second collections of samples. To deskew the legs of a differential signal with respect to each other, corresponding features within the first and second collections are identified and a difference is taken between them. The differential skew can then be applied to correct measurements of differential signals.

7017087, Mar 21, 2006

Dec 29, 2000

09/751633

Michael C. Panis - Brookline MA, US
Bradford B. Robbins - Wellesley MA, US

Teradyne, Inc. - Boston MA

G01R 31/28

714716

A system and method for economically yet thoroughly testing serial ports of electronic devices includes a receiver and a transmitter. The receiver is coupled to a TX line of a device under test for receiving an input serial bit stream from the device under test. The transmitter is coupled to a RX line of the device under test for providing an output serial bit stream to the device under test. The receiver is coupled to the transmitter for establishing a loopback connection. A time distortion circuit is interposed between the receiver and the transmitter, for adding predetermined amounts of timing distortion to the output serial bit stream. In addition, a selector is interposed between the receiver and the transmitter, for selecting between the receiver and a direct input. The direct input provides an algorithmic test signal that differs from the input serial bit stream received by the receiver. The direct input thus allows a tester to exercise the device under test with a test signal that differs from the signal that the device under test generates.

7337377, Feb 26, 2008

Dec 22, 2005

11/315974

Michael C. Panis - Brookline MA, US
Bradford B. Robbins - Wellesley MA, US

Teradyne, Inc. - North Reading MA

G01R 31/28

714716

A system and method for economically yet thoroughly testing serial ports of electronic devices includes a receiver and a transmitter. The receiver is coupled to a TX line of a device under test for receiving an input serial bit stream from the device under test. The transmitter is coupled to a RX line of the device under test for providing an output serial bit stream to the device under test. The receiver is coupled to the transmitter for establishing a loopback connection. A time distortion circuit is interposed between the receiver and the transmitter, for adding predetermined amounts of timing distortion to the output serial bit stream. In addition, a selector is interposed between the receiver and the transmitter, for selecting between the receiver and a direct input. The direct input provides an algorithmic test signal that differs from the input serial bit stream received by the receiver. The direct input thus allows a tester to exercise the device under test with a test signal that differs from the signal that the device under test generates.

7349818, Mar 25, 2008

Nov 10, 2005

11/272027

Michael Panis - Somerville MA, US

Teradyne, Inc. - North Reading MA

G01R 29/26

702 69

A method of determining frequency components of jitter in a waveform is provided. The method includes conducting a plurality of locally-in-order strobings of the waveform. Changing the acquisition time associated with each locally-in-order strobing. Measuring jitter associated with each locally-in-order strobing and determining jitter as a function of frequency based on the measured jitter associated with each change of acquisition time.

7519490, Apr 14, 2009

Jan 25, 2008

12/020027

Michael Panis - Somerville MA, US

Teradyne, Inc. - North Reading MA

G01R 29/26

702 69

A method of determining frequency components of jitter in a waveform is provided. The method includes strobing a waveform having a repetitive pattern. Forming a locally-in-order strobing scheme of a representative one of the repetitive pattern including subsets of locally-in-order strobes. Locating transition regions in the subsets of locally-in-order strobes. Determining random jitter associated for each transition region and determining jitter as a function of frequency.

7606675, Oct 20, 2009

Jan 25, 2008

12/020020

Michael Panis - Somerville MA, US

Teradyne, Inc. - North Reading MA

G01R 29/26

702 69

A jitter frequency determining system is provided that includes a comparator, a clock source, a latching circuit, a memory device and a processor. The comparator is adapted to receive at least one output signal from a device under test and compare the output signal to an expected signal. The output signal has a repeating pattern. The clock source is adapted to produce a sampling clock based on user inputs. The clock source is further adapted to change the time between locally-in-order strobes to adjust the measurement bandwidth. The latching circuit is adapted to obtain samples of the output signal according to the sampling clock. The memory device is adapted to store the sampled data. The processor is adapted to analyze the stored data to determine jitter and to express jitter as a function of frequency.

7668235, Feb 23, 2010

Nov 10, 2005

11/271507

Michael Panis - Somerville MA, US
Steve Munroe - Lakeway TX, US
John Pane - Tigard OR, US

Teradyne - Boston MA

H04B 3/46
H04B 17/00
H04Q 1/20

375226, 375371, 702 69, 324750, 324755, 324759, 324763, 324764

A method of jitter measurement is provided and includes sampling a device-under-test (DUT) output signal, having a repeating pattern, using an asynchronous clock over a desired period of time and mapping the samples onto a single period of the repeating pattern. Each period of the repeating pattern is sampled at least twice. A sampling frequency of the asynchronous clock is based on user inputs. Sampling the DUT signal comprises capturing logical state information representing each edge of a single period of the DUT signal at least once. The method further includes, separating the samples into subsets and mapping the sample subsets onto a single period of the repeating pattern wherein the samples within a particular subset are mapped to a set of times which are in the same order as in which the samples were obtained, processing the samples within each subset independently of samples in other subsets, and combining results of the processed subsets and processing the combined results of the subsets.