Michael Ricchetti DeceasedColorado Springs, CO

6957371, Oct 18, 2005

May 10, 2002

10/142556

Michael Ricchetti - Nashua NH, US
Christopher J. Clark - Durham NH, US

Intellitech Corporation - Durham NH

G01R031/28

714733, 714724, 714735, 714726, 365201

An embedded electronic system built-in self-test controller architecture that facilitates testing and debugging of electronic circuits and in-system configuration of programmable devices. The system BIST controller architecture includes an embedded system BIST controller, an embedded memory circuit, an embedded IEEE 1149. 1 bus, and an external controller connector. The system BIST controller is coupled to the memory circuit and the IEEE 1149. 1 bus, and coupleable to an external test controller via the external controller connector. The external test controller can communicate over the IEEE 1149. 1 bus to program the memory and/or the system BIST controller circuitry, thereby enabling scan vectors to be debugged by the external test controller and then downloaded into the memory for subsequent application to a unit under test by the system BIST controller.

6988232, Jan 17, 2006

Apr 9, 2002

10/119060

Michael Ricchetti - Nashua NH, US
Christopher J. Clark - Durham NH, US

Intellitech Corporation - Durham NH

G06F 11/00

714736

An architecture that provides stimulus data and verifies the response of multiple electronic circuits substantially in parallel for optimized testing, debugging, or programmable configuration of the circuits. The architecture includes a test bus, a primary test controller connected to the bus, and a plurality of local test controllers connected to the bus, in which each local test controller is coupleable to a respective circuit. The primary test controller sends stimulus data and expected response data over the bus to the respective local test controllers to perform parallel testing, debugging or programmable configuration of the circuits. Each local test controller applies the stimulus data and verifies the circuit response against the expected response data. Further, each local test controller stores the result of the verification for later retrieval by the primary test controller.

7406638, Jul 29, 2008

Jul 22, 2004

10/896646

Christopher J. Clark - Durham NH, US
Michael Ricchetti - Nashua NH, US

Intellitech Corporation - Durham NH

G01R 31/28

714724

A system and method for maximizing the throughput of test and configuration in the manufacture of electronic circuits and systems. The system employs a tester having a flexible parallel test architecture with expandable resources that can accommodate a selected number of units under test (UUTs). The parallel test architecture is configurable to accept separate banks or partitions of UUTs, thereby enabling the system to obtain an optimal or maximum achievable throughput of test and configuration for the UUTs. The system determines an optimal or maximum achievable throughput by calculating a desired number N of UUTs to be tested/configured in parallel. Testing or configuring this desired number of UUTs in parallel allows the handling time to be balanced with the test and configuration times, thereby resulting in the maximum achievable throughput.

7467342, Dec 16, 2008

May 16, 2005

11/130332

Michael Ricchetti - Nashua NH, US
Christopher J. Clark - Durham NH, US

Intellitech Corporation - Durham NH

G01R 31/3187
G01R 31/40

714733, 714736

An embedded electronic system built-in self-test controller architecture that facilitates testing and debugging of electronic circuits and in-system configuration of programmable devices. The system BIST controller architecture includes an embedded system BIST controller, an embedded memory circuit, an embedded IEEE 1149. 1 bus, and an external controller connector. The system BIST controller is coupled to the memory circuit and the IEEE 1149. 1 bus, and coupleable to an external test controller via the external controller connector. The external test controller can communicate over the IEEE 1149. 1 bus to program the memory and/or the system BIST controller circuitry, thereby enabling scan vectors to be debugged by the external test controller and then downloaded into the memory for subsequent application to a unit under test by the system BIST controller.

7574637, Aug 11, 2009

Nov 23, 2005

11/286915

Michael Ricchetti - Nashua NH, US
Christopher J. Clark - Durham NH, US

Intellitech Corporation - Durham NH

G01R 31/28
G11C 29/00

714724, 365201

A Parallel Test Architecture (PTA) is provided that facilitates concurrent test, debug or programmable configuration of multiple electronic circuits (i. e. , simultaneously). The PTA includes a communications path, a primary test controller, and a number of local test controllers. The primary controller provides stimulus, expected, and mask data to the local controllers over the communications path. The local controllers apply the stimulus data to the electronic circuits, receive resultant data generated by the circuits in response to the stimulus data, and locally verify the resultant data against the expected data substantially concurrently. When the communications path is implemented as an IEEE 1149. 1 (JTAG) test bus, the primary controller can provide the expected and mask data to the local controllers over the TDO and TRSTN lines while the TAP controllers of the electronic circuits are in the Shift-IR or Shift-DR state to enable concurrent testing over a traditional five wire multi-drop IEEE 1149. 1 test bus.

8443331, May 14, 2013

Aug 10, 2010

12/853940

Sophocles R. Metsis - Wakefield MA, US
Michael Ricchetti - Nashua NH, US

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 17/50

716136

A system includes multiple TAP controllers that can be independently powered up and down. When a first TAP controller is powered up from a powered-down state while a second TAP controller is already in a powered-up state, the first TAP controller is reset causing the first TAP controller to enter a reset state in response to the power-up of a module on which the first TAP controller is disposed. The first TAP controller enters an idle state and its control signal is gated to hold the first TAP controller in the idle state until the second TAP controller enters the idle state. Subsequently, the first TAP controller is released such that the control signal supplied to the first and second TAP controllers are equal, thereby synchronizing the first TAP controller and the second TAP controller.

2003014, Jul 24, 2003

Jan 21, 2003

10/347904

Michael Ricchetti - Nashua NH, US
Christopher Clark - Durham NH, US

INTELLITECH CORPORATION

G06F017/60
H04K001/00

713/201000, 705/001000, 713/182000

A system and method of licensing electronic circuit designs within target electronic circuits or devices that allows secure delivery and reliable accounting of the licensed circuit designs on a per-usage basis. The method includes determining whether an electronic circuit design is licensable for use within a target electronic circuit by verifying licensing information included in a set of predetermined vectors associated with the electronic circuit design. In the event it is determined that the electronic circuit design is licensable for use within the target electronic circuit, the set of vectors is applied to the target electronic circuit by a licensing controller. Next, in response to a predetermined event, an attribute of the licensing information is updated to indicate the licensed use of the electronic circuit design within the target circuit. The licensing system allows IP core providers and IP core users to account for the use of licensed electronic circuit designs on a per-usage basis with higher accuracy, thereby providing increased assurance that the electronic circuit designs are being licensed in a manner that is fair to all parties.

6594802, Jul 15, 2003

Nov 20, 2000

09/716583

Michael Ricchetti - Nashua NH
Christopher J. Clark - Durham NH
Bulent I. Dervisoglu - Mountain View CA

Intellitech Corporation - Durham NC

G06F 1750

716 4, 716 16, 714727

An access interface for accessing electrical nodes of an electronic circuit for programming, testing, and debugging the electronic circuit. The access interface includes a protocol generator and a data generator that may be programmed to apply control and/or data sequences directly to the electronic circuit. The access interface performs operational commands based upon a plurality of states included in a programmable state machine. By suitably programming the protocol generator, the data generator, and the state machine, electrical nodes of the electronic circuit can be accessed in reduced time using a reduced number of operations. The access interface is controlled by a test resource apparatus, which communicates with the electronic circuit connected to the access interface. The access interface may be implemented as a downloadable circuit, e. g. , it may be programmed into a programmable logic device by the test resource apparatus.