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Michael Douglas Wedlake, 4911805 Terraza Cir, Austin, TX 78726

Known as:
Michael D Wedlake Mikeal D Wedlake
Related to:
Elizabeth A Wedlake Patricia Wedlake 39

Michael Wedlake Phones & Addresses

11805 Terraza Cir, Austin, TX 78726   

11805 Terraza Cir #51, Austin, TX 78726   

6503 Bluff Springs Rd, Austin, TX 78744   

Guilderland, NY   

Albany, NY   

Baton Rouge, LA   

Mesa, AZ   

3500 Bronco Bend Loop, Austin, TX 78744   

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Michael Douglas Wedlake

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Work

Company: Samsung foundry Feb 2014 Position: Staff engineer - process integration, technology development, rmg and mol team

Education

Degree: Master of Business Administration, Masters School / High School: The University of Texas at Austin - Red Mccombs School of Business 2006 to 2009 Specialities: Marketing

Skills

Semiconductors • Spc • Design of Experiments • Semiconductor Industry • Process Simulation • Process Engineering • Cross Functional Team Leadership • Metrology • R&D • Failure Analysis • Manufacturing • Jmp • Thin Films • Yield • Statistical Process Control • Business Strategy • Engineering • Continuous Improvement • Negotiation • New Business Development • Research and Development • Market Research • Silicon • Process Integration • Root Cause Analysis • Cvd • Chemical Vapor Deposition

Interests

Playing Soccer • Political Science • Politics • Cartooning • Drawing • History

Industries

Semiconductors
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Michael Wedlake resumes & CV records

Resumes

Michael Wedlake Photo 14

Staff Engineer - Process Integration, Technology Development, Rmg And Mol Team

Location:
Austin, TX
Industry:
Semiconductors
Work:
Samsung Foundry
Staff Engineer - Process Integration, Technology Development, Rmg and Mol Team Globalfoundries May 2011 - Jan 2014
Member of Technical Staff - Cmp Research Engineer Texas Instruments Jul 2010 - Jan 2011
Cmp Process Engineer Advanced Hydro Inc. Sep 2009 - Jul 2010
Strategic Project Manager Spansion Dec 2005 - Feb 2009
Senior Manufacturing Engineer Rfmicron, Inc. Jun 2008 - Aug 2008
Intern Amd Dec 2000 - Dec 2005
Manufacturing Engineer Ii Freescale Semiconductor Jun 1997 - Aug 1997
Summer Intern Elf Atochem 1994 - 1995
Summer Intern, 1994 and 1995
Education:
The University of Texas at Austin - Red Mccombs School of Business 2006 - 2009
Master of Business Administration, Masters, Marketing Georgia Institute of Technology 1997 - 2000
Master of Science, Masters, Chemical Engineering The University of Texas at Austin 1993 - 1997
Bachelors, Bachelor of Science, Chemical Engineering Manheim Township Middle School 1986 - 1988
Baton Rouge Magnet High School
Skills:
Semiconductors, Spc, Design of Experiments, Semiconductor Industry, Process Simulation, Process Engineering, Cross Functional Team Leadership, Metrology, R&D, Failure Analysis, Manufacturing, Jmp, Thin Films, Yield, Statistical Process Control, Business Strategy, Engineering, Continuous Improvement, Negotiation, New Business Development, Research and Development, Market Research, Silicon, Process Integration, Root Cause Analysis, Cvd, Chemical Vapor Deposition
Interests:
Playing Soccer
Political Science
Politics
Cartooning
Drawing
History

Publications & IP owners

Us Patents

Probe Apparatus, A Process Of Forming A Probe Head, And A Process Of Forming An Electronic Device

US Patent:
8179153, May 15, 2012
Filed:
Jul 17, 2008
Appl. No.:
12/174743
Inventors:
Michael D. Wedlake - Austin TX, US
Assignee:
Spansion LLC - Sunnyvale CA
International Classification:
G01R 31/20
US Classification:
32475401
Abstract:
A probing apparatus includes a set of conductors configured to contact a surface of a workpiece simultaneously. A processor activates subsets of the conductors to determine a four-point-probe parameter, wherein the subset is less than the set of conductors. Another subset determines another four-point-probe parameter. The set of conductors remain in contact with the surface of the workpiece during and between activating each subset. A process of forming a probe head includes a probe substrate and associated conductive leads. An insulating layer is formed over the probe substrate and patterned to expose the leads. Conductors, connected to the leads, are formed over the insulating layer and define a probing area of a least 250 cm. A process of forming an electronic device includes contacting a surface of a workpiece using conductors. Subset of the conductors are activated to determine four-point-probe parameters at different areas of the workpiece.

Processes For Forming Electronic Devices Including Polishing Metal-Containing Layers

US Patent:
8232209, Jul 31, 2012
Filed:
Feb 11, 2011
Appl. No.:
13/025979
Inventors:
Christopher E. Brannon - Pflugerville TX, US
Michael Wedlake - Austin TX, US
Chris A. Nauert - Austin TX, US
Assignee:
Spansion LLC - Sunnyvale CA
International Classification:
H01L 21/302
US Classification:
438692
Abstract:
A process of forming an electronic device can include providing a workpiece. The workpiece can include a substrate, an interlevel dielectric overlying the substrate, a refractory-metal-containing layer over the interlevel dielectric, and a first metal-containing layer over the refractory-metal-containing layer. The first metal-containing layer can include a metal element other than a refractory metal element. The process further includes polishing the first metal-containing layer and the refractory-metal-containing layer as a continuous action to expose the interlevel dielectric. In one embodiment, the metal element can include copper, nickel, or a noble metal. In another embodiment, polishing can be performed using a selectivity agent to reduce the amount of the interlevel dielectric removed.

Processes For Forming Electronic Devices Including Polishing Metal-Containing Layers

US Patent:
2009011, May 7, 2009
Filed:
Nov 2, 2007
Appl. No.:
11/934628
Inventors:
Christopher E. Brannon - Pflugerville TX, US
Michael Wedlake - Austin TX, US
Chris A. Nauert - Austin TX, US
Assignee:
SPANSION LLC - Sunnyvale CA
International Classification:
H01L 21/44
B24B 29/02
US Classification:
438656, 438692, 451 57, 451 59, 257E21476
Abstract:
A process of forming an electronic device can include providing a workpiece. The workpiece can include a substrate, an interlevel dielectric overlying the substrate, a refractory-metal-containing layer over the interlevel dielectric, and a first metal-containing layer over the refractory-metal-containing layer. The first metal-containing layer can include a metal element other than a refractory metal element. The process further includes polishing the first metal-containing layer and the refractory-metal-containing layer as a continuous action to expose the interlevel dielectric. In one embodiment, the metal element can include copper, nickel, or a noble metal. In another embodiment, polishing can be performed using a selectivity agent to reduce the amount of the interlevel dielectric removed.

Finfet Device With A Substantially Self-Aligned Isolation Region Positioned Under The Channel Region

US Patent:
2016019, Jun 30, 2016
Filed:
Mar 8, 2016
Appl. No.:
15/063633
Inventors:
- Grand Cayman, KY
Vimal K. Kamineni - Albany NY, US
Abner F. Bello - Clifton Park NY, US
Nicholas V. LiCausi - Watervliet NY, US
Wenhui Wang - Clifton Park NY, US
Michael Wedlake - Albany NY, US
Jason R. Cantone - Mechanicville NY, US
International Classification:
H01L 29/78
H01L 29/10
H01L 29/51
H01L 29/06
Abstract:
One illustrative device disclosed herein includes, among other things, a semiconductor substrate, a fin structure, a gate structure positioned around a portion of the fin structure in the channel region of the device, spaced-apart portions of a second semiconductor material positioned vertically between the fin structure and the substrate, wherein the second semiconductor material is a different semiconductor material than that of the fin, and a local channel isolation material positioned laterally between the spaced-apart portions of the second semiconductor material and vertically below the fin structure and the gate structure, wherein the local channel isolation material is positioned under at least a portion of the channel region of the device.

Methods And Systems For Chemical Mechanical Planarization Endpoint Detection Using An Alternating Current Reference Signal

US Patent:
2015037, Dec 24, 2015
Filed:
Jun 23, 2014
Appl. No.:
14/311761
Inventors:
- Grand Cayman, KY
Michael Wedlake - Austin TX, US
International Classification:
H01L 21/66
H01L 21/67
B24B 37/04
H01L 21/306
B24B 37/005
B24B 37/27
Abstract:
Methods, non-transitory computer readable media, and systems are provided for detecting an endpoint of a chemical mechanical planarization (CMP) process on a semiconductor substrate. The method comprises generating a reference signal, generating a first signal with which to control a CMP system, generating a second signal using a combination of the first signal and the reference signal, commanding the CMP system with the second signal, generating a response signal that indicates an operational characteristic of the CMP system that is responsive to the second signal and a friction property of the semiconductor substrate, and filtering the response signal using the reference signal to determine the endpoint of the CMP process.

Methods Of Forming Substantially Self-Aligned Isolation Regions On Finfet Semiconductor Devices And The Resulting Devices

US Patent:
2015029, Oct 15, 2015
Filed:
May 29, 2015
Appl. No.:
14/725663
Inventors:
- Grand Cayman, KY
Vimal K. Kamineni - Albany NY, US
Abner F. Bello - Clifton Park NY, US
Nicholas V. LiCausi - Watervliet NY, US
Wenhui Wang - Clifton Park NY, US
Michael Wedlake - Albany NY, US
Jason R. Cantone - Mechanicville NY, US
International Classification:
H01L 21/8234
H01L 21/308
H01L 29/78
H01L 21/3213
H01L 21/02
H01L 29/66
H01L 21/762
Abstract:
One method disclosed includes performing a selective etching process through a gate cavity to selectively remove a portion of a first semiconductor material relative to a second layer of a second semiconductor material and a substrate so as to thereby define a space between the second semiconducting material and the substrate, filling substantially all of the space with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become the channel region of the FinFET device.

Methods Of Forming Substantially Self-Aligned Isolation Regions On Finfet Semiconductor Devices And The Resulting Devices

US Patent:
2015012, May 14, 2015
Filed:
Nov 13, 2013
Appl. No.:
14/079159
Inventors:
- Grand Cayman, KY
Vimal K. Kamineni - Albany NY, US
Abner F. Bello - Clifton Park NY, US
Nicholas V. LiCausi - Watervliet NY, US
Wenhui Wang - Clifton Park NY, US
Michael Wedlake - Albany NY, US
Jason R. Cantone - Mechanicville NY, US
Assignee:
GLOBALFOUNDRIES Inc. - Grand Cayman
International Classification:
H01L 27/088
H01L 29/06
H01L 29/165
H01L 21/8234
US Classification:
257192, 438283
Abstract:
One method disclosed includes performing a selective etching process through a gate cavity to selectively remove a portion of a first semiconductor material relative to a second layer of a second semiconductor material and a substrate so as to thereby define a space between the second semiconducting material and the substrate, filling substantially all of the space with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become the channel region of the FinFET device.

Hard Mask Removal During Finfet Formation

US Patent:
2014027, Sep 18, 2014
Filed:
Mar 13, 2013
Appl. No.:
13/799508
Inventors:
- Grand Cayman, KY
Michael D. Wedlake - Albany NY, US
Assignee:
GLOBALFOUNDRIES INC. - Grand Cayman
International Classification:
H01L 21/306
H01L 21/3105
US Classification:
438692
Abstract:
An approach for polishing-based hard mask removal during FinFET device formation is provided. In a typical embodiment, an initial device will be provided with a set of fins (e.g., silicon (Si)), a set of fin caps (e.g., silicon nitride (SiN)), and an oxide layer. A post-oxide planarizing and thinning polishing will first be performed (e.g., using a Silica-based slurry) to thin/reduce the oxide layer. A stop-on-nitride polishing will then be performed (e.g., using a Ceria-based slurry) to reduce the oxide layer to a top surface of the fin caps. Still yet, a stop-on-silicon polishing will be performed (e.g., using a Ceria-based slurry) to remove the set of fin caps and to reduce the oxide layer to a top surface to the set of fins.

Possible Relatives

Daniel P Wedlake  Kathleen M Wedlake  Richard Wedlake  Susan P Wedlake  Terry Wedlake  Thomas R Wedlake  Michael C Last  Michael C Johnson  Michael F Stamps  Michael Stan 

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