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Ming N Fang, 592210 Firerock Ave, Richland, WA 99352

Related to:
Lin V Zhong 53 Huanzi Wang 49

Ming Fang Phones & Addresses

2210 Firerock Ave, Richland, WA 99352   

1318 Jubilee St, Richland, WA 99352    509-3969406   

Portland, OR   

4054 Hooch River Trl, Suwanee, GA 30024   

Hillsboro, OR   

Columbus, GA   

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Ming Fang resumes & CV records

Resumes

Ming Fang Photo 38

China Chief Representative/Senior Or Consultant At Paragon Decision Technology

Position:
Chief Representative/Senior OR Consultant at Paragon Decision Technology
Location:
Shanghai City, China
Industry:
Information Technology and Services
Work:
Paragon Decision Technology - Shanghai, China since Feb 2012
Chief Representative/Senior OR Consultant Paragon Decision Technology - Bellevue, Washington May 2007 - Apr 2012
AIMMS Specialist/OR Analyst ALSTOM Grid - Redmond, Washington Feb 2010 - 2011
AIMMS Optimization Consultant AREVA T&D - Redmond, Washington Jun 2007 - Jan 2010
AIMMS Optimization Consultant Thomas J. Edwards Learning Center, University at Buffalo Sep 2005 - May 2007
Teaching Assistant/Instructor
Education:
State University of New York College at Buffalo 2007
MS, Industrial Engineering/Operations Research State University of New York College at Buffalo 2005
BS(Magna Cum Laude), Electrical Engineering
Skills:
Mathematical Modeling, Optimizations, Data Analysis, Mathematical Programming, Operations Research, CPLEX
Ming Fang Photo 39

China Chief Representative/Senior Or Consultant At Paragon Decision Technology

Position:
Chief Representative/Senior OR Consultant at Paragon Decision Technology
Location:
Shanghai City, China
Industry:
Information Technology and Services
Work:
Paragon Decision Technology - Shanghai, China since Feb 2012
Chief Representative/Senior OR Consultant Paragon Decision Technology - Bellevue, Washington May 2007 - Apr 2012
AIMMS Specialist/OR Analyst ALSTOM Grid - Redmond, Washington Feb 2010 - 2011
AIMMS Optimization Consultant AREVA T&D - Redmond, Washington Jun 2007 - Jan 2010
AIMMS Optimization Consultant Thomas J. Edwards Learning Center, University at Buffalo Sep 2005 - May 2007
Teaching Assistant/Instructor
Education:
State University of New York College at Buffalo 2005 - 2007
MS, Industrial Engineering/Operations Research State University of New York College at Buffalo 2003 - 2005
BS(Magna Cum Laude), Electrical Engineering Saginaw Valley State University 2001 - 2003
Skills:
Mathematical Modeling, Optimizations, Data Analysis, Mathematical Programming, Operations Research, CPLEX
Ming Fang Photo 40

Principal Engineer

Location:
Pasco, WA
Industry:
Oil & Energy
Work:
Bechtel Corporation
Principal Engineer Infinia Technology Corp Oct 2008 - Oct 2010
Senior Lead Engineer Intel Corporation 2002 - 2008
Senior Material Engineer
Education:
Missouri University of Science and Technology 1993 - 1998
Doctorates, Doctor of Philosophy, Engineering
Skills:
Design of Experiments, Engineering, Materials, Engineering Management, Failure Analysis, Process Engineering, Semiconductors, Project Engineering, R&D, Root Cause Analysis, Process Simulation, Fmea, Materials Science, Six Sigma, Design For Manufacturing, Spc, Finite Element Analysis, Ansys
Ming Fang Photo 41

Ming Fang

Ming Fang Photo 42

Ming Huang Fang

Skills:
C++, Microsoft Excel, Teaching, C, English, Public Speaking, Outlook, Microsoft Office, Microsoft Word, Strategic Planning, Negotiation, Java, Research, Photoshop, Event Planning
Ming Fang Photo 43

Ming Fang

Ming Fang Photo 44

Ming Fang

Location:
United States
Ming Fang Photo 45

Ming Fang

Location:
United States

Publications & IP owners

Us Patents

Large Bumps For Optical Flip Chips

US Patent:
6933171, Aug 23, 2005
Filed:
Oct 21, 2003
Appl. No.:
10/691136
Inventors:
Ming Fang - Portland OR, US
Valery Dubin - Portland OR, US
Daoqiang Lu - Chandler AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L021/44
H01L021/48
H01L021/50
H01L023/48
H01L023/52
US Classification:
438108, 257778, 22818022
Abstract:
The invention provides bumps between a die and a substrate with a height greater than or equal to a height of a waveguide between the die and the substrate. The bumps may be formed on a die prior to that die being singulated from a wafer.

Method And Apparatus For Filling Interlayer Vias On Ferroelectric Polymer Substrates

US Patent:
7001782, Feb 21, 2006
Filed:
Dec 29, 2003
Appl. No.:
10/747824
Inventors:
Daniel C. Diana - Portland OR, US
Ebrahim Andideh - Portland OR, US
Richard M. Steger - Beaverton OR, US
Valery Dubin - Portland OR, US
Ming Fang - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 21/00
US Classification:
438 3, 438 99, 438637, 257 40, 257295
Abstract:
Some embodiments for a method to fill interlayer vias with a suitable metal in a ferroelectric polymer memory die to reduce the step height and improve the thermal and electrical properties of the via. The method uses an electroless plating method to fill the vias, which is compatible with the ferroelectric polymer memory die processing temperature limits. The resulting process produces via fill metal plugs in the ferroelectric memory die, which allows for the deposition of a thin metal layer over the vias, while at the same time improving the electrical and thermal properties of the vias. Other embodiments are described and claimed herein.

Under Bump Metallization Layer To Enable Use Of High Tin Content Solder Bumps

US Patent:
7064446, Jun 20, 2006
Filed:
Mar 29, 2004
Appl. No.:
10/812464
Inventors:
John P. Barnak - Beaverton OR, US
Gerald B. Feldewerth - Beaverton OR, US
Ming Fang - Portland OR, US
Kevin J. Lee - Beaverton OR, US
Harry Y. Liang - Portland OR, US
Seshu V. Sattiraju - Portland OR, US
Margherita Chang - Portland OR, US
Andrew W. H. Yeoh - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 23/48
H01L 23/52
H01L 29/40
US Classification:
257779, 257780, 257781, 257782, 257783
Abstract:
Apparatus and methods of fabricating an under bump metallization structure including an adhesion layer abutting a conductive pad, a molybdenum-containing barrier layer abutting the adhesion layer, a wetting layer abutting the molybdenum-containing barrier layer, and high tin content solder material abutting the wetting layer. The wetting layer may be substantially subsumed in the high content solder forming an intermetallic compound layer. The molybdenum-containing barrier layer prevents the movement of tin in the high tin content solder material from migrating to dielectric layers abutting the conductive pad and potentially causing delamination and/or attacking any underlying structures, particularly copper structures, which may be present.

Large Bumps For Optical Flip Chips

US Patent:
7279720, Oct 9, 2007
Filed:
Jun 8, 2004
Appl. No.:
10/864188
Inventors:
Ming Fang - Portland OR, US
Valery Dubin - Portland OR, US
Daoqiang Lu - Chandler AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 33/00
US Classification:
257 98, 257E33067
Abstract:
The invention provides bumps between a die and a substrate with a height greater than or equal to a height of a waveguide between the die and the substrate. The bumps may be formed on a die prior to that die being singulated from a wafer.

Tin Deposition

US Patent:
7314543, Jan 1, 2008
Filed:
Oct 14, 2003
Appl. No.:
10/685659
Inventors:
Ming Fang - Portland OR, US
Valery M. Dubin - Portland OR, US
Scott M. Haight - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
C25D 5/02
C25D 7/12
C25D 3/30
C25D 3/32
US Classification:
205302, 205300, 205123, 205157
Abstract:
A device includes an integrated circuit and a deposited tin in electrical contact with a portion of the integrated circuit. The deposited tin is formed by electrodeposition from a bath. The deposited tin includes a residue characteristic of the bath. The bath includes a bath-soluble tin compound, a strong acid, and a sulfopropylated anionic surfactant. In another aspect, a composition includes between approximately 20 and 40 grams per liter of one of stannous methane sulfonate, stannous sulfate, and a mixture thereof, between approximately 100 and 200 grams per liter of one of methanesulfonic acid, sulfuric acid, and a mixture thereof, and between approximately 1 and 2 grams per liter of one or more polyethyleneglycol alkyl-3-sulfopropyl diethers. In another aspect, a method includes electroplating tin with a current density of greater than approximately 30 mA/cm2 and a plating efficiency of greater than approximately 95%.

Capping Copper Bumps

US Patent:
7391112, Jun 24, 2008
Filed:
Jun 1, 2005
Appl. No.:
11/142971
Inventors:
Jianxing Li - Albuquerque NM, US
Ming Fang - Portland OR, US
Ting Zhong - Tigard OR, US
Fay Hua - San Jose CA, US
Kevin J. Lee - Beaverton OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 23/48
H01L 23/52
H01L 29/40
US Classification:
257737, 257738, 257772, 257779, 257E23021, 257E23033, 257E23069, 257E21508
Abstract:
A structure including a substrate, a copper bump formed over the substrate, and a barrier layer comprising an alloy of at least one of iron and nickel, formed over the copper bump, and methods to make such a structure.

Forming A Barrier Layer In Interconnect Joints And Structures Formed Thereby

US Patent:
7416980, Aug 26, 2008
Filed:
Mar 11, 2005
Appl. No.:
11/078611
Inventors:
Ting Zhong - Tigard OR, US
Valery Dubin - Portland OR, US
Ming Fang - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 21/44
US Classification:
438685, 438643, 438648, 438672, 257E21295, 257E21508
Abstract:
Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a barrier layer on a substrate, wherein the barrier layer comprises molybdenum; and forming a lead free interconnect structure on the barrier layer.

Method For Constructing Contact Formations

US Patent:
7442634, Oct 28, 2008
Filed:
Dec 21, 2004
Appl. No.:
11/019857
Inventors:
Valery M. Dubin - Portland OR, US
Ming Fang - Portland OR, US
Kevin J. Lee - Beaverton OR, US
Yuehai Liang - Portland OR, US
Margherita Chang - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 21/44
US Classification:
438613, 438612, 438676
Abstract:
According to one aspect of the invention, a method for forming contact formations is provided. A substrate may be placed in an electrolytic solution. The substrate may have an exposed conductive portion and the electrolytic solution may include a plurality of metallic ions and an accelerator. The accelerator may include at least one of bis-(sodium sulfopropyl)-disulfide and 3-mercapto-1-propanesulfonic acid-sodium salt. A voltage may be applied across the electrolytic solution and the conductive portion of the substrate to cause the metallic ions to be changed into metallic particles and deposited on the conductive portion. The electrolytic solution may also include a protonated organic additive. The electrolytic solution may also include an acid and a surfactant. The acid may include at least one of sulfuric acid, methane sulfonic acid, benzene sulfonic acid, and picryl sulfonic acid.

Possible Relatives

Cynthia F Fang  David Fang  Aaron E Fang  Dong Y Fang  Elaine Y Fang  Evelyn Y Fang  Fang W Fang  Ming Whitehead  Ming N Lau  Ming Le 

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