Naresh R Shanbhag, 584404 Trostshire Cir, Champaign, IL 61822

7298226, Nov 20, 2007

May 24, 2006

11/420195

Naresh Shanbhag - Champaign IL, US
Hyeon Min Bae - Champaign IL, US
Jinki Park - Plano TX, US
Paul Suppiah - San Jose CA, US

Finisar Corporation - Sunnyvale CA

H03B 1/00

331177V, 331175, 331185, 331 36 C

A noise tolerant voltage controlled oscillator is described. The voltage controlled oscillator include a varactor element as part of an LC tank circuit. The varactor element is biased by a bias signal and a bias-dependent control signal. The bias-dependent control signal tunes the LC tank circuit. Because the control signal is bias-dependent, noise and other deleterious influences do not cause the varactor element to deviate in capacitance. Instead, the bias-dependent control signal is a tuning signal that is centered around the bias signal, which allows the varactor element to provide a constant capacitance in the event of a varying bias signal.

7592869, Sep 22, 2009

Sep 17, 2007

11/856681

Hyeon Min Bae - Champaign IL, US
Naresh Ramnath Shanbhag - Champaign IL, US
Jonathan B. Ashbrook - Homer IL, US

Finisar Corporation - Sunnyvale CA

H03F 3/45

330254, 330283, 330300

An electronic amplifier circuit that provides improved gain control linearity characteristics resulting from having a controllable field effect transistor (FET) acting as a degeneration resistance (degeneration resistance FET) and a controllable load resistance FET. The overall gain function of the amplifier exhibits improved linearity in part due to the presence of the load FET, which tends to cancel the nonlinear behavior emanating from the degeneration FET. The circuit also includes a control circuit for generating non-linear control signals that are responsive to process characteristics of the FETs, such that the degeneration resistance FET and load resistance FETs may be controlled more consistently and independently from process variations.

7609102, Oct 27, 2009

May 24, 2006

11/420196

Naresh Shanbhag - Champaign IL, US
Hyeon Min Bae - Champaign IL, US
Jinki Park - Plano TX, US
Paul Suppiah - San Jose CA, US

Finisar Corporation - Sunnyvale CA

H03H 11/16

327231, 327 3, 327 12, 327237, 327243, 375371, 375373, 375375

A phase detector apparatus and method used for clock recovery from a data signal is provided. The phase detector provides phase correction signals to a clock signal generator, where the phase correction signals are only generated if a predetermined data sample pattern is observed. In particular, the predetermined data sample pattern is preferably a transition from one to zero. Thus, transitions from zero to one will not provide a valid phase update output signal, even though a transition has occurred. In other embodiments the predetermined data sample pattern is preferably a one to zero transition preceded by an additional logic one sample.

7695085, Apr 13, 2010

Sep 17, 2007

11/856680

Hyeon Min Bae - Champaign IL, US
Naresh Ramnath Shanbhag - Champaign IL, US
Jonathan B. Ashbrook - Homer IL, US

Finisar Corporation - Sunnyvale CA

B41J 29/38
H03F 3/45

347 10, 330254

A variable gain amplifier and offset cancellation loop circuit and methods for tracking and correcting DC offset errors that may vary in accordance with the gain of the variable gain amplifier. The circuit is designed to provide tracking of rapid changes in the offset error while maintaining a desired overall frequency response of the combined variable gain amplifier and offset loop. The offset loop cancellation circuit has a wide enough bandwidth to allow the offset cancellation loop to track rapid changes in offset errors that result from rapid changes to the amplifier's gain setting. A control circuit is provided to prevent the large offset cancellation loop bandwidth from having a detrimental effect on the amplifier's overall bandwidth when the amplifier is set to high levels of forward gain by adjusting the offset cancellation loop gain as the forward gain of the amplifier is altered.

7750831, Jul 6, 2010

Feb 28, 2008

12/039424

Heyon Min Bae - Champaign IL, US
Naresh Ramnath Shanbhag - Champaign IL, US
Andrew C. Singer - Champaign IL, US
Jonathan B. Ashbrook - Homer IL, US

Finisar Corporation - Sunnyvale CA

H03M 1/00

341126, 341155

Methods and systems are provided for an improved phase detector utilizing analog-to-digital converter (ADC) components. In an embodiment, the method includes from an ADC having a sampling clock signal that determines sampling instants, obtaining a first comparison value between an analog signal and a first threshold voltage at a first sampling instant, and obtaining a second comparison value between the analog signal and a second threshold voltage at a second sampling instant. The method further includes, from a supplemental circuit, obtaining a third comparison value between the analog signal and a third threshold voltage at a third sampling instant between the first and second sampling instants. The method further includes processing the first, second, and third comparison values to determine a phase relationship between the analog signal and the sampling clock.

7834692, Nov 16, 2010

Sep 17, 2007

11/856691

Hyeon Min Bae - Champaign IL, US
Naresh Shanbhag - Champaign IL, US
Jonathan B. Ashbrook - Homer IL, US

Finisar Corporation - Sunnyvale CA

H03F 3/45
G01R 19/04

330254, 327 61

A peak detector circuit that responds rapidly to power transients, and yet is able to avoid interpreting data fluctuations as power transients by generating dual peak signals from an amplifier's differential output signal, where the dual peak signals have data ripple components that tend to cancel one another. The system and methods permit the peak detectors to be much more responsive to power transients by expanding their bandwidth (shortening the time constants) to the point that low frequency data components affect the individual peak detector signals, but the effects are cancelled out when the individual components are added together. The peak detector described herein may be used in an AGC system to provide ripple-free gain control signals, while rapidly following any power transients in transmitted signals.

8068742, Nov 29, 2011

Jul 10, 2008

12/171201

Christopher R. Cole - Redwood City CA, US
Daniel Mahgerefteh - Palo Alto CA, US
Andrew C. Singer - Champaign IL, US
Naresh Ramnath Shanbhag - Champaign IL, US

Finisar Corporation - Sunnyvale CA

H04B 10/00

398152, 398141, 398139, 398184, 398205

A high-speed optical transmitter comprises multiple digital lanes that are provided to a bank of digital-to-analog converters. The analog signals are then used to Phase Shift Keyed (PSK) modulation using a Chirp Managed Laser (CML)-based transmitter, and potentially using dual polarization. A corresponding optical receiver receives the sequence of optical signals at a demodulator. For each polarization, the demodulator includes a corresponding demodulation channel that is configured to demodulate that polarization component of the optical signal into one or more signal components. Each of these signal components is converted into a corresponding digital signal using a corresponding analog-to-digital converter. In the case of higher-order PSK modulation (e. g. , 8PSK or higher), for each polarization, the analog converter has a lower sampling rate than for QPSK modulation.

8102938, Jan 24, 2012

Apr 22, 2008

12/107581

Jonathan B. Ashbrook - Homer IL, US
Andrew C. Singer - Champaign IL, US
Naresh R. Shanbhag - Champaign IL, US
Robert J. Drost - Champaign IL, US

Finisar Corporation - Sunnyvale CA

H04L 27/00

375295

A system and method is disclosed for controlling signal conditioning parameters and a sampling parameter controlling conversion of a received signal to digital sampled values prior to decoding. The sampled values are decoded according to a comparison with expected values calculated according to a model of a transmission channel. The model is also updated from time to time by comparing the expected values with actual sampled values. Variation of the expected values over time is calculated. One or more of the signal conditioning parameters and the sampling parameter are adjusted according to a numerical minimization method such that the system BER is reduced.