Neal Berger, 6622623 Woodridge Ct, Cupertino, CA 95014

7009886, Mar 7, 2006

Jul 19, 2004

10/893809

Neal Berger - Cupertino CA, US
George Chia-Jung Chang - Cupertino CA, US
Pearl Po-Yee Cheng - Los Altos CA, US
Anne Pao-Ling Koh - Sunnyvale CA, US

Silicon Storage Technology, Inc. - Sunnyvale CA

G11C 16/06

36518525, 36518521, 365240

An integrated circuit memory device has an array of memory cells arranged in a plurality of rows and columns and a plurality of row lines and a plurality of column lines. Cells arranged in the same row are connected by a common row line, and cells arranged in the same column are connected by a common column line. Each cell in the array is addressed by an address signal which has a plurality of bits. A sense amplifier circuit is connectable to one or more of the plurality of column lines of the array. An address input terminal receives in series the plurality of bits of the address signal. Each of the column lines is connectable to a pre-charge voltage, in response to a read command. A decoder circuit receives the address signal and decodes the address signal as each of the plurality of bits is received and disconnects certain of the column lines to the pre-charge voltage in response to the decoding, and activates the sense amplifier circuit after all of the plurality of bits of the address signal are received.

7027348, Apr 11, 2006

Aug 17, 2004

10/921754

Neal Berger - Cupertino CA, US
George Chia-Jung Chang - Cupertino CA, US
Pearl Po-Yee Cheng - Los Altos CA, US
Anne Pao-Ling Koh - Sunnyvale CA, US

Silicon Storage Technology, Inc. - Sunnyvale CA

G11C 8/00

36523003, 365207, 365221, 365240

An integrated circuit memory device has a plurality of memory cells arranged in a plurality of arrays. Each array has a plurality of rows, and a plurality of column lines, and a plurality of row lines connecting to the memory cells in each array. The memory cell in an array is addressable by a column line and a row line. A column address decoder receives a column address signal and selects one or more column lines of each array in response. A row address decoder receives a row address signal and selects a row line of each array in response. The memory device also has a plurality (k) of sense amplifiers, with one sense amplifier associated with each array, connectable to one or more column lines of the array and receives a signal therefrom supplied from an addressed memory cell. The memory device further has a register; and a control circuit. The control circuit receives a read command, and a clock signal, and in response to the read command activates a first plurality (j) of the plurality (k) of sense amplifiers (j

8031519, Oct 4, 2011

Jun 16, 2009

12/485359

Virgile Javerliac - Grenoble, FR
Neal Berger - Cupertino CA, US
Kenneth Mackay - St. Martin le Vinoux, FR
Jean-Pierre Nozieres - Le Sappey-en-Chartreuse, FR

Crocus Technology S.A. - Grenoble Cedex

G11C 11/15
G11C 7/00

365173, 36518916, 365171

A memory unit with one field line; at least two thermally-assisted switching magnetic tunnel junction-based magnetic random access memory cells, each cell comprising a magnetic tunnel junction having an insulating layer disposed between a magnetic storage layer and a magnetic reference layer; wherein a selection transistor is connected to the magnetic tunnel junction; the one field line is used for passing a field current for switching a magnetization of the storage layer of the magnetic tunnel junctions of the cells. A magnetic memory device can be formed by assembling an array of the memory units, wherein at least two adjacent magnetic tunnel junctions of the cells can be addressed simultaneously by the field line. The memory unit and magnetic memory device have a reduced surface area. Magnetic memory devices with an increased density of memory units can be fabricated resulting in lower die fabrication cost and lower power consumption.

8169815, May 1, 2012

Apr 6, 2009

12/418747

Neal Berger - Cupertino CA, US

Crocus Technology S.A. - Grenoble Cedex

G11C 11/00

365158, 365171, 365173

Magnetic random access memory (MRAM) cell with a thermally assisted switching writing procedure and methods for manufacturing and using same. The MRAM cell includes a magnetic tunnel junction that has at least a first magnetic layer, a second magnetic layer, and an insulating layer disposed between the first and a second magnetic layers. The MRAM cell further includes a select transistor and a current line electrically connected to the junction. The current line advantageously can support a plurality of MRAM operational functions. The current line can fulfill a first function for passing a first portion of current for heating the junction and a second function for passing a second portion of current in order to switch the magnetization of the first magnetic layer.

8218349, Jul 10, 2012

May 21, 2010

12/784848

Neal Berger - Cupertino CA, US
Mourad El Baraji - Saint Martin d'Heres, FR

Crocus Technology SA - Grenoble Cedex

G11C 11/00

365148, 365158

The present disclosures concerns a register cell comprising a differential amplifying portion containing a first inverter coupled to a second inverter such as to form an unbalanced flip-flop circuit; a first and second bit line connected to one end of the first and second inverter, respectively; and a first and second source line connected to the other end of the first and second inverter, respectively; characterized by the register cell further comprising a first and second magnetic tunnel junction electrically connected to the other end of the first and second inverter, respectively. The shift register disclosed herein can be made smaller than conventional shift registers and power consumption during the write and read operation of the shift registers can be low. The shift register disclosed herein can be made smaller than conventional shift registers and power consumption during the write and read operation of the shift registers can be low.

8441844, May 14, 2013

Jun 8, 2011

13/155669

Mourad El Baraji - Sunnyvale CA, US
Neal Berger - Cupertino CA, US

Crocus Technology SA - Grenoble Cedex

G11C 11/00

365158, 365148, 365171, 977935

A method of writing in a memory device comprising a plurality of MRAM cells, each cell including a magnetic tunnel junction having a resistance that can be varied during a write operation when heated at a high threshold temperature; a plurality of word lines connecting cells along a row; and a plurality of bit lines connecting cells along a column; the method comprising supplying a bit line voltage to one of the bit lines and a word line voltage to one of the word lines for passing a heating current through the magnetic tunnel junction of a selected cell; said word line voltage is a word line overdrive voltage being higher than the core operating voltage of the cells such that the heating current has a magnitude that is high enough for heating the magnetic tunnel junction at the predetermined high threshold temperature. The memory device can be written with low power consumption.

8467234, Jun 18, 2013

Feb 8, 2011

13/023442

Neal Berger - Cupertino CA, US
Mourad El Baraji - Sunnyvale CA, US

Crocus Technology Inc. - Santa Clara CA

G11C 11/00

365158, 365170, 365171, 365173, 365130

A magnetic random access memory cell includes a sense layer, a storage layer, and a spacer layer disposed between the sense layer and the storage layer. During a write operation, the storage layer has a magnetization direction that is switchable between m directions to store data corresponding to one of m logic states, with m>2. During a read operation, the sense layer has a magnetization direction that is varied, relative to the magnetization direction of the storage layer, to determine the data stored by the storage layer.

8488372, Jul 16, 2013

Jun 10, 2011

13/158316

Mourad El Baraji - Sunnyvale CA, US
Neal Berger - Cupertino CA, US

Crocus Technology Inc. - Santa Clara CA

G11C 11/00

365158, 365171, 257421, 257422

A magnetic random access memory (MRAM) cell includes a storage layer, a sense layer, and a spacer layer between the storage layer and the sense layer. A field line is magnetically coupled to the MRAM cell to induce a magnetic field along a magnetic field axis, and at least one of the storage layer and the sense layer has a magnetic anisotropy axis that is tilted relative to the magnetic field axis. During a write operation, a storage magnetization direction is switchable between m directions to store data corresponding to one of m logic states, with m>2, where at least one of the m directions is aligned relative to the magnetic anisotropy axis, and at least another one of the m directions is aligned relative to the magnetic field axis. During a read operation, a sense magnetization direction is varied, relative to the storage magnetization direction, to determine the data stored by the storage layer.