Nersi H Nazari, 6599 Belbrook Way, Menlo Park, CA 94027

6456208, Sep 24, 2002

Jun 30, 2000

09/607904

Nersi Nazari - Cupertino CA
Andrei Vityaev - Santa Clara CA

Marvell International, Ltd. - Hamilton

H03M 700

341 59, 341 81

In this invention a thirty three bit word is encoded from a thirty two bit word to conform to RLL coding constraints. A parity bit is added to the coded word after coding is complete. With the parity bit inserted the code satisfies a minimum Hamming weight of nine and no more than eleven consecutive zeros and no more than eleven consecutive zeros in both the odd and even interleaves. A table of âbadâ eight bit sequences is used to compare the odd and even interleaves of the right and left halves of the input word that is being encoded. If a âbadâ sequence is found, its position in the table points to a second table containing a four bit replacement code that is inserted into the coded output word. Flag bits in the output coded word are set to indicate the violation of the coding constraints and provide a means by which a decoder can be used to reverse the process and obtain the original input word.

6526530, Feb 25, 2003

Dec 22, 1999

09/470170

Nersi Nazari - Cupertino CA
Andrei Vityaev - Santa Clara CA

Marvell International, Ltd. - Hamilton

G06F 1100

714701, 714758

Method and apparatus for encoding data using check bits for additional data protection, in addition to the time-varying maximum transition run code which eliminates data patterns producing long runs of consecutive transitions. The check bits are inserted into codewords in preselected locations. The time-varying maximum transition run code does not permit more than j transitions beginning from an even-numbered sample period and does not permit more than j+l transitions beginning from an odd-numbered sample period, wherein j 1. This time-varying maximum transition run constraint is preserved even after the check bits are inserted, regardless of the bit values of the check bits.

6888897, May 3, 2005

Apr 27, 2000

09/559186

Nersi Nazari - Cupertino CA, US
Zining Wu - Los Altos CA, US
Greg Burd - San Jose CA, US

Marvell International Ltd. - Hamilton

H04L023/02
H09L005/12

375262, 375341, 714752, 714758

A transmitter is provided for transmitting data to a communication channel and a receiver receives the data from the communication channel. The transmitter comprises an encoder to encode data and a linear block encoder to encode data encoded by the encoder. The receiver comprises a soft channel decoder to decode the data, and a soft linear block code decoder to decode data decoded by the soft channel decoder. In the first iteration, the soft channel decoder decodes data received by the receiver. In succeeding iterations, the soft channel decoder decodes the data received by the receiver and utilizes information from the soft linear block decoder from an immediate preceding iteration. A decision circuit selects an output of the soft linear block decoder if an evaluated criterion is less than a threshold, or an output of the soft channel decoder if the evaluated criterion is greater than the threshold. A decoder decodes an output of the threshold check circuit.

7340003, Mar 4, 2008

Aug 27, 2004

10/927325

Nersi Nazari - Cupertino CA, US
Zining Wu - Los Altos CA, US
Greg Burd - San Jose CA, US

Marvell International Ltd. - Hamilton

H04L 5/12
H04L 23/02

375262, 714746, 714752, 714758, 714800, 714801, 714802, 714803, 714804, 708530, 708531

A storage system for storing data on a storage medium includes an encoder, a linear block encoder, a write circuit, a read circuit, a channel decoder, and a soft linear block code decoder. In a first iteration, the channel decoder decodes data read by the read circuit. In succeeding iterations, the channel decoder decodes the data read by the read circuit and utilizes information decoded by the soft linear block decoder from an immediately preceding iteration. The storage system includes a threshold check circuit to select (i) an output of the soft linear block code decoder if the number of parity-check violations has a first relationship with respect to a threshold, or (ii) an output of the channel decoder if the number of violations has a second relationship with respect to the threshold. The storage system includes a decoder to decode an output of the threshold check circuit.

8136005, Mar 13, 2012

Oct 9, 2007

11/973500

Nersi Nazari - Cupertino CA, US
Zining Wu - Los Altos CA, US
Greg A Burd - San Jose CA, US

Marvell International Ltd. - Hamilton

H03M 13/00
H03M 13/03

714752, 714755, 714786, 714795

A storage system comprises a linear block encoder. A write circuit writes an output of the linear block encoder to a storage medium. A read circuit reads data from the storage medium. A channel decoder decodes the data. A soft linear block code decoder that decodes the data decoded by the channel decoder. The channel decoder decodes the data read in a first iteration. In a subsequent iteration the channel decoder decodes the data read by the read circuit and utilizes information decoded by the soft linear block code decoder. A threshold check circuit selects an output of the soft linear block code decoder if a number of parity check violations has a first relationship with respect to a threshold, or an output of the channel decoder if the number of parity check violations has a second relationship with respect to the threshold.

5809081, Sep 15, 1998

May 20, 1996

8/650700

Razmik Karabed - San Jose CA
Nersi Nazari - Cupertino CA

Mitel Semiconductor Americas Inc. - San Jose CA

H04L 512
H04L 2302

345263

A system comprises an encoder, a precoder, a PR channel, a detector, and a decoder. An input signal is received by the encoder. The encoder generates a code string by adding one or more bits and outputs the code string to the precoder. The encoder applies such encoding such that the code string after being modified by the precoder has a pre-selected parity structure. The encoder provides a systematic encoding scheme in which many of the encoded bits are the same as the input bits used to generate the encoded bits. This systematic approach of the present invention provides an encoder that is easy to implement because a majority of the bits are directly "feed through" and non-trivial logic circuits are only needed to generate the control bits. The systematic encoding also dictates a decoder that is likewise easy to construct and can be implemented in a circuit that simply discards the control bit. The encoder preferably comprises a serial-to-parallel converter, a code generator and a parallel-to-serial converter.

6084535, Jul 4, 2000

Jan 30, 1997

8/791687

Razmik Karabed - San Jose CA
Nersi Nazari - Cupertino CA
Andrew Popplewell - Manchester, GB
Isaiah A. Carew - Santa Cruz CA

Mitel Semiconductor Americas Inc. - San Jose CA

H03M 500

341 58

A system comprises an encoder, a precoder, a PRML channel, a detector, and a decoder. An input signal is received by the encoder. The encoder generates a code string by adding one or more bits and outputs the code string to the precoder. The encoder applies encoding such that the code string after passing through the precoder has a Hamming distance greater than one to eliminate error events with a small distance at the output of the PRML channel. The present invention also provides codes that after precoding have Hamming distance of 2 and 0 mod 3 number of ones. These codes when used over a PRML channel in an interleaved manner preclude +/-(. . . 010-10. . . ) error events and error events +/-(. . . 01000-10. . . ). The code string also has a predetermined minimum number of ones at the output of the PRML channel to help derive a clock from the input signal.

5809080, Sep 15, 1998

Oct 10, 1995

8/541675

Razmik Karabed - San Jose CA
Nersi Nazari - Cupertino CA

Mitel Semiconductor Americas Inc. - San Jose CA

H04L 512

375263

A system and method includes an encoder and noise predictive Viterbi detector tuned such that error events with small values of the unique distance metrics are eliminated so that the error rate is enhanced. The system includes an encoder, a modulator, a PR channel and a detector. An input signal is input to the encoder. The encoder preferably encodes the input string with an even weight code to generate a code string thereby providing high code rates that are easy to implement. The output of the encoder is coupled to the input of the PR channel. The PR channel preferably comprises a filter and a noise source coupled to form a channel, a sampler, a low pass filter and an equalizer. The output of the channel is input to the low pass filter. The output of the low pass filter is coupled by the sampler to the input of the equalizer. Finally, the output of the equalizer is coupled to the input of the detector.