Nicholas G Cafaro, 516315 NW 71St Ter, Parkland, FL 33067

6897687, May 24, 2005

Mar 6, 2003

10/382696

Nicholas Cafaro - Coconut Creek FL, US
Robert Stengel - Pompano Beach FL, US

Motorola, Inc. - Schaumburg IL

H03B021/00

327105

A frequency generator () includes a direct digital synthesizer () having an accumulator (or ) for providing an interim output and a digital interpolator () for interpolating the interim output to provide an output signal with reduced electromagnetic interference. The digital interpolator can include at least one converter among a digital-to-phase converter () or a digital-to-time converter (). The frequency generator can further include a digitally programmable spreading function () applied to an input of the direct digital synthesizer.

6959397, Oct 25, 2005

Jun 18, 2003

10/464239

Nicholas Giovanni Cafaro - Coconut Creek FL, US
Robert E. Stengel - Pompano Beach FL, US

Motorola, Inc. - Schaumburg IL

G06F001/04

713503, 713401, 713500, 375371

A programmable skew clock signal generator has a frequency generator circuit () consistent with the invention produces an output signal Ffrom a reference signal FA frequency accumulator () is preloaded with a preload value Pand receives one reference signal cycle as a clock signal, receives a constant Kas an input thereto, with the frequency accumulator () having a maximum count Kand producing an overflow output. A phase accumulator () is preloaded with a preload value Pand receives one overflow cycle output from the frequency accumulator () as a clock signal and receives a phase offset constant Cas an input thereto. The phase accumulator () has a maximum count Cand produces a phase accumulator () output. A delay line () is clocked by the reference signal Fand produces a plurality of delayed reference clock signals at a plurality of tap outputs. A tap selecting circuit () receives the phase accumulator output and selects at least one of the tap outputs in response thereto to produce an output Fwhose phase shift φrelative to F is a function of Pand P.

7031372, Apr 18, 2006

Oct 13, 2004

10/964114

Andrew T. Tomerlin - Coral Springs FL, US
Nicholas G. Cafaro - Coconut Creek FL, US
Robert E. Stengel - Pompano Beach FL, US

Motorola, Inc. - Schaumburg IL

H04L 27/30

375146, 375150, 713100, 713321, 713500, 714739, 327116, 327119

A circuit consistent with certain embodiments of the present invention has a source of N reference clock frequencies (), where N is an integer greater than one. N frequency extender circuits () receive the N reference clock frequencies and generating N frequency extended output clock signals therefrom. A plurality of N seed slewers () produce N seed update values. A plurality of N seed registers () each receive one of the N seed update values and produce N seed masks therefrom. A plurality of N logic circuits () each receive one of the N seed masks and one of the N frequency extended output clock signals. Each of the N logic circuits () produce a pseudorandom sequence from the seed mask and the frequency extended output clock signal. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.

7114069, Sep 26, 2006

Apr 22, 2003

10/420221

Andrew Tomerlin - Coral Springs FL, US
Nicholas Giovanni Cafaro - Coconut Creek FL, US
Robert E. Stengel - Pompano Beach FL, US

Motorola, Inc. - Schaumburg IL

G06F 9/00

713100, 326 39

A reconfigurable processor circuit () consistent with certain embodiments of the present invention has an array of configurable circuit blocks (), wherein certain of the configurable circuit blocks () comprise one of configurable arithmetic logic units and clocked digital logic circuits. A control processor () configures a function of a plurality of the configurable circuit blocks. A memory () stores program instructions used by the control processor (). A multiple frequency generator () receives a reference clock and synthesizes the plurality of clock signals therefrom, each clock signal being configured in frequency by the control processor (). A timing control circuit () receives the plurality of clock signals, allocates the plurality of clock signals of different frequency among the plurality of circuit blocks and routes the clock signals to the circuit blocks, wherein the timing control circuit () operates under control of the control processor ().

7251468, Jul 31, 2007

Jul 14, 2004

10/890691

Charles R. Ruelke - Margate FL, US
Nicholas G. Cafaro - Coconut Creek FL, US
Robert E. Stengel - Pompano Beach FL, US

Motorola, Inc. - Schaumburg IL

H04B 1/10

455296, 455310, 455311

A dynamically matched mixer system () for use in a direct conversion radio frequency (RF) receiver includes a frequency generator () that includes plurality of dividers () for providing differential local oscillator reference sources (F and F) and mitigation frequency reference sources (F and F) from reference oscillator (). A mixer () mixes the differential local oscillator reference sources (F and F) and the mitigation frequency reference sources (F and F) while dynamic matching units () are used for receiving the mitigation frequency reference sources and matching switching parameters of differential input signals (I and I) and differential baseband output signals (I and I). The frequencies of the mitigation frequency reference sources (F and F) are selected so as to establish a non-integer relationship to the reference oscillator () for mitigating the occurrence of interference with F and F.

7315215, Jan 1, 2008

Mar 8, 2006

11/370689

Nicholas G. Cafaro - Coconut Creek FL, US
Thomas L. Gradishar - Boynton Beach FL, US
Robert E. Stengel - Pompano Beach FL, US

Motorola,, Inc. - Schaumburg IL

H03L 7/08

331 16, 327158

Improvement of quantization errors that arise in a delay line with finite resolution. A direct digital synthesizer (DDS), which contains a numerically controlled oscillator (NCO) and a digital-to-phase converter (DPC), is placed in the feedback loop of a phase locked loop (PLL). The DDS is used as a fractional divider of the voltage controlled oscillator (VCO) frequency, such that the reference frequency of the DDS is made variable. Alignment of the edges provided by the DDS delay line may then be adjusted. Mismatch errors in the DDS delay line are reduced by utilizing independently tunable delay elements.

7570096, Aug 4, 2009

Sep 26, 2007

11/861860

Nicholas G. Cafaro - Coconut Creek FL, US
Thomas L. Gradishar - Boynton Beach FL, US
Robert E. Stengel - Pompano Beach FL, US

Motorola, Inc. - Schaumburg IL

H03H 11/26

327262, 327264, 327270, 327271, 327272, 327288

Improvement of quantization errors that arise in a delay line with finite resolution. A direct digital synthesizer (DDS), which contains a numerically controlled oscillator (NCO) and a digital-to-phase converter (DPC), is placed in the feedback loop of a phase locked loop (PLL). The DDS is used as a fractional divider of the voltage controlled oscillator (VCO) frequency, such that the reference frequency of the DDS is made variable. Alignment of the edges provided by the DDS delay line may then be adjusted. Mismatch errors in the DDS delay line are reduced by utilizing independently tunable delay elements.

7620133, Nov 17, 2009

Nov 8, 2004

10/983447

Nicholas G. Cafaro - Coconut Creek FL, US
Thomas L. Gradishar - Boynton Beach FL, US
Robert E. Stengel - Pompano Beach FL, US

Motorola, Inc. - Schaumburg IL

H04L 7/00

375354, 375371, 327141, 327144, 327161, 327269, 327271

A DPC () includes: a frequency source () for generating a clock signal; a delay line () for receiving the clock signal and generating phase-shifted clock signals at output taps; a digital control device () for generating a control signal; and a windowing and selection circuit for generating the output signal, that includes sequential logic devices () and a combining network. A method for use in a DPC includes: receiving () a control signal based on a desired output signal that identifies a first output tap on the delay line; based on the control signal, selecting () at least two output taps on the delay line for receiving at least two different phase-shifted clock signals; and generating () an output signal based on the control signal and the received phase-shifted clock signals that is substantially the desired output signal.