Nicholas N Wade, 571919 SE 10Th Ave UNIT 4142, Fort Lauderdale, FL 33316

6725349, Apr 20, 2004

Mar 13, 2003

10/389092

Brian K. Langendorf - Benicia CA
James M. Dodd - Shingle Springs CA
Nicholas D. Wade - Portland OR

Intel Corporation - Santa Clara CA

G06F 1200

711170, 711 5, 711105, 711167, 714719, 714718, 36518901, 365233, 36523305

A method and apparatus for optimizing control on a bank to bank basis of a memory subsystem having a plurality of memory banks which are installed with different types of dynamic random access memory (DRAM) devices is presented. The present invention includes an improved DRAM controller comprises a set of configuration registers which store configuration bits corresponding to each memory bank in the main memory that is populated with the DRAM devices. The memory controller also includes a detection logic which together with a memory bank decode logic enables the memory controller determine whether a particular memory bank is populated with a page mode DRAM or an extended data out DRAM. The preferred embodiment also includes a column address strobe state machine which automatically controls timing requirements of both type of DRAM devices installed in the main memory to quickly and efficiently handle access requests.

5404482, Apr 4, 1995

Jun 22, 1992

7/902122

Rebecca L. Stamm - Wellesley MA
Nicholas D. Wade - Folsom CA

Digital Equipment Corporation - Maynard MA

G06F 1200
G06F 1300

395425

A processor and method for preventing access to a locked memory block in a multiprocessor computer system. The processor has a cache memory and records a memory lock in a content-addressable memory separate from the cache memory. Preferably, outstanding cache fills are recorded in the same content addressable memory as memory locks, and a memory lock or an outstanding cache fill delays the execution of a cache coherency request upon the same memory block. When a cache coherency request is received from another processor, the address of the cache coherency request is compared to addresses stored in the content addressable memory, and when there is a match, a bit in the matching entry is set to indicate a delayed request that is executed after the lock is unlocked or the cache is refilled. In a specific embodiment, a memory lock or an outstanding cache fill also stalls a processor read or write to the same memory block.

5155843, Oct 13, 1992

Jun 29, 1990

7/547597

Rebecca L. Stamm - Boston MA
R. Iris Bahar - Belmont MA
Michael Callander - Hudson MA
Linda Chao - Chelmsford MA
Derrick R. Meyer - Watertown MA
Douglas Sanders - Framingham MA
Richard L. Sites - Boylston MA
Raymond Strouble - Southbridge MA
Nicholas Wade - Marlborough MA

Digital Equipment Corporation - Maynard MA

G06F 1100

395575

A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. Macroinstruction pipelining is employed (instead of microinstruction pipelining), with queueing between units of the CPU to allow flexibility in instruction execution times. A wide bandwidth is available for memory access; fetching 64-bit data blocks on each cycle. A hierarchical cache arrangement has an improved method of cache set selection, increasing the likelihood of a cache hit. A writeback cache is used (instead of writethrough) and writeback is allowed to proceed even though other accesses are suppressed due to queues being full. A branch prediction method employs a branch history table which records the taken vs. not-taken history of branch opcodes recently used, and uses an empirical algorithm to predict which way the next occurrence of this branch will go, based upon the history table. A floating point processor function is integrated on-chip, with enhanced speed due to a bypass technique; a trial mini-rounding is done on low-order bits of the result, and if correct, the last stage of the floating point processor can be bypassed, saving one cycle of latency.

5347648, Sep 13, 1994

Jul 15, 1992

7/914777

Rebecca L. Stamm - Wellesley MA
Ruth I. Bahar - Lincoln NE
Raymond L. Strouble - Charlton MA
Nicholas D. Wade - Folsom CA
John H. Edmondson - Cambridge MA

Digital Equipment Corporation - Maynard MA

G06F 1100

395575

Writeback transactions from a processor and cache are fed to a main memory through a writeback queue, and non-writeback transactions from the processor and cache are fed to the main memory through a non-writeback queue. When a cache error is detected, an error transition mode (ETM) is entered that provides limited use of the data in the cache; a read or write request for data not owned in the cache is made to the main memory instead of the cache, even when the data is valid in the cache, although owned data is read from the cache. In ETM, when the processor makes a first write request to data not owned in the cache followed by a second write request to data owned in the cache, write data of the first write request is prevented from being received by the main memory after write data of the second request while permitting writeback of the data owned by the cache. Preferably this is done by sending the write requests from the processor through the non-writeback queue, and when a write request accesses data in a block of data owned by the cache, disowning the block of data in the cache and writing the disowned block of data back to the main memory.

5404483, Apr 4, 1995

Jun 22, 1992

7/902156

Rebecca L. Stamm - Wellesley MA
Ruth I. Bahar - Lincoln NE
Nicholas D. Wade - Folsom CA

Digital Equipment Corporation - Maynard MA

G06F 1200
G06F 1300

395425

A processor and method for delaying the processing of cache coherency transactions during outstanding cache fills in a multi-processor system using a shared memory. A first processor fetches data having a specified address by addressing a cache memory, and when the specified address is not in the cache, saving the specified address in a fill address memory, and sending a fill request to the shared memory. Before return of fill data, the first processor receives a cache coherency request including the specified address from a second processor requesting invalidation of an addressed block of data. The first processor responds by checking whether the fill address memory includes the specified address, and upon finding the specified address in the fill address memory, delaying execution of the cache coherency request until the fill data is returned, and when the fill data is returned, using the fill data without retaining a validated block of the fill data in the cache. In a preferred embodiment, the fill memory is a content-addressable memory including a plurality of entries, and each entry has a fill address, an ownership fill bit (OREAD), an ownership-read invalidate pending bit (OIP), and a read invalidate pending bit (RIP). The OIP or RIP bit is set when execution of a cache coherency request is delayed, and these bits are read upon completion of a fill to execute the delayed request.