Norman N Rubin Deceased4 Random Ln, Andover, MA 01810

6968542, Nov 22, 2005

Feb 23, 2001

09/791912

Richard J. Bagley - Arlington MA, US
Dean M. Deaver - Sterling MA, US
Chris L. Reeve - Brookline MA, US
Norman Rubin - Cambridge MA, US

Hewlett-Packard Development Company, L.P. - Houston TX

G06F009/45

717139, 717141, 712236

A method of identifying pseudo-invariant instructions in computer program hot paths, comprising the steps of creating an intermediate representation of a hot path in a software buffer, executing instructions in the program image for the computer program until a hot path is detected, copying computer machine state and computer processor register contents to a context in memory, and using this context to compute an output a plurality of times for each instruction in the hot path using an interpreter that emulates the computer processor. Results of the interpreter computations are stored with the frequency count for each unique output in a table that is readable by a program optimizer. Frequency counts for each instruction are compared with a pseudo-invariant threshold to classify an instruction as pseudo-invariant.

7281122, Oct 9, 2007

Jan 14, 2004

10/756853

Norman Rubin - Cambridge MA, US
Andrew Gruber - Arlington MA, US

ATI Technologies Inc. - Markham, Ontario

G06F 11/10

712226, 712235, 712233, 712234

A method and apparatus for nested control flow includes a processor having at least one context bit. The processor includes a plurality of arithmetic logic units for performing single instruction multiple data (SIMD) operations. The method and apparatus further includes a first memory device storing a plurality of instructions wherein each of the plurality of instructions includes a plurality of extra bits. The processor is operative to execute the instructions based on the extra bits and in conjunction with a context bit. The method and apparatus further includes a second memory device, such as a general purpose register operably coupled to the processor, the second memory device receiving an incrementing counter instruction upon the execution of one of the plurality of instructions. As such, the method and apparatus allows for nested control flow through a single context bit in conjunction with instructions having a plurality of extra bits.

7568191, Jul 28, 2009

Jan 30, 2004

10/768804

Norman Rubin - Cambridge MA, US
Richard Bagley - Arlington MA, US

ATI Technologies, Inc. - Markham, ON

G06F 9/45

717151, 717141, 717146

A method and apparatus for superword register value numbering includes hashing an operation code and the value numbers of a plurality of sources to generate a flint hash value. The method and apparatus further includes retrieving an operation value number from the first hash table based on the first hash value. The method and apparatus further includes generating a result value number based on a previous bit hash value and the operation value number. The result value number is a combination of the operation value numbers for each component having a live indicator (e. g. , a false write mask value) and a previous value numbers for the components without the live indicator (e. g. , a true write mask value). Thereupon, the method and apparatus includes searching a second hash table using the result value number. As such, the method and apparatus provides using two separate hash tables for value numbering with superword instructions.

7568193, Jul 28, 2009

Jan 28, 2004

10/767480

Norman Rubin - Cambridge MA, US
Myron King - Cambridge MA, US

ATI Technologies, Inc. - Markham, ON

G06F 9/45

717159, 717140, 717151, 717154

A method and apparatus for SSA dead code elimination includes examining a first instruction off a worklist, wherein the first instruction includes previous link and a write mask and the first instruction is an SSA instruction. The method and apparatus further includes examining at least one second instruction of the machine code, wherein the at least one second instructions are sources of the first instruction and the at least one second instructions are SSA instruction. In the method and apparatus, each of the at least one second instructions include a previous link and a write mask. The method and apparatus further includes determining if any components within a particular field of the at least one second instruction are live. If none of the components are live, the method and apparatus provides for deleting the second instruction from the machine code as it is determined that this instruction is extraneous, dead code.

7774765, Aug 10, 2010

Feb 7, 2006

11/348746

Norman Rubin - Cambridge MA, US
William L. Licea-Kane - Arlington MA, US

ATI Technologies Inc. - Markham, Ontario

G06F 9/45
G06T 15/50

717144, 717155, 717156, 717157, 717159, 345426

A method and apparatus for use in compiling data for a program shader identifies within data representing control flow information an area operator definition instruction statement located outside the data dependent control flow structures. The method identifies within one of the data dependent branches at least one area operator use instruction statement that has the resultant of the area operator definition instruction statement as an operand. After identifying the area operator use instruction statement, the area operator definition instruction statement is placed within the data dependent branch.

2002017, Nov 14, 2002

Feb 23, 2001

09/792783

Chris Reeve - Brookline MA, US
Dean Deaver - Sterling MA, US
Norman Rubin - Cambridge MA, US

G06F009/44

717/127000

A method of debugging a dynamic computer program optimizer beginning with creating two copies of the contents of the registers in a computer processor. One copy is loaded into pseudo-registers and the other is saved for a verification test. A test sequence comprising an intermediate representation of a program hot path is loaded in a software buffer and executed. Register and memory read and write commands in the test sequence are executed with the pseudo-registers and a memory buffer. The second copy of the register contents are then loaded back to the processor registers. The program hot path is executed and register and memory read and write commands are executed with the processor registers and system memory. The contents of the registers and memories are compared and if the contents match, the test sequence is valid. The test sequence may also comprise a translated copy of the program hot path.

2013015, Jun 20, 2013

Dec 15, 2011

13/327443

Norman RUBIN - Cambridge MA, US
Michael Mantor - Orlando FL, US

Advanced Micro Devices, Inc. - Sunnyvale CA

G06T 1/00

345501

Provided is a method for processing system calls from a GPU to a CPU. The method includes a GPU storing a plurality of tasks in a memory, with each task representing a function to be performed on the CPU. The method also includes generating a CPU interrupt, and processing of the stored plurality of tasks by the CPU.

2013015, Jun 20, 2013

Dec 15, 2011

13/326587

Norman Rubin - Cambridge MA, US
Gang Chen - Southborough MA, US

ADVANCED MICRO DEVICES, INC. - Sunnyvale CA

G06F 9/38

712244, 712E0906

A function in source code is processed by a compiler for execution on a graphics processing unit, wherein the function includes an exception handling structure. An exception raising block is converted into a first control flow and an exception handler block is converted into a second control flow. The first control flow includes setting an exception raised indicator and finding an exception handler to process the raised exception. The exception raised indicator remains set until an appropriate exception handler is found. The second control flow includes clearing the exception raised indicator and processing the exception.