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Norman R Scheinberg, 7524 New St, South River, NJ 08882

Norman Scheinberg Phones & Addresses

24 New St, South River, NJ 08882    732-2578874    732-3904866   

New York, NY   

24 New St, South River, NJ 08882    732-2578874   

Work

Position: Protective Service Occupations

Education

Degree: Bachelor's degree or higher

Mentions for Norman R Scheinberg

Norman Scheinberg resumes & CV records

Resumes

Norman Scheinberg Photo 10

Professor

Location:
24 New St, South River, NJ 08882
Industry:
Higher Education
Work:
Anadigics Sep 1985 - Jan 2010
Ic Designer
City College of New York Sep 1985 - Jan 2010
Professor
Education:
Ccny School of Education 1973 - 1979
Doctorates, Doctor of Philosophy, Electronics, Electronics Engineering, Philosophy
Massachusetts Institute of Technology 1970 - 1971
Masters, Electronics Engineering, Electronics
Roosevelt High School 1963 - 1966
Massachusetts Institute of Technology
Ccny School of Education
Skills:
Research, Public Speaking, Microsoft Office, Curriculum Development, Curriculum Design, Editing, Science
Norman Scheinberg Photo 11

Professor

Location:
New York, NY
Industry:
Semiconductors
Work:
City College of New York
Professor

Publications & IP owners

Us Patents

Architecture And Method For Improving Efficiency Of A Class-A Power Amplifier By Dynamically Scaling Biasing Current Thereof As Well As Synchronously Compensating Gain Thereof In Order To Maintain Overall Constant Gain Of The Class-A Power Amplifier At All Biasing Configurations Thereof

US Patent:
7535297, May 19, 2009
Filed:
Feb 27, 2007
Appl. No.:
11/711292
Inventors:
Xinghao Chen - Endwell NY, US
Yanbo Tian - Summit NJ, US
Norman Scheinberg - South River NJ, US
International Classification:
H03G 3/20
US Classification:
330129
Abstract:
An architecture and method for improving efficiency of a Class-A power amplifier by dynamically scaling biasing current thereof as well as synchronously compensating gain thereof in order to maintain overall constant gain of the Class-A power amplifier at all biasing configurations thereof. A biasing-current switching-network is operatively connected to the back-end block of the Class-A power amplifier. A gain-control switching-network is operatively connected to a front-end block of the Class-A power amplifier. A detector-and-control block is operatively connected to an output of the back-end block of the Class-A power amplifier, and samples a signal that is then compared with reference signals to determine switching configurations in the biasing-current switching-network and the gain-control switching network when the signal is processed through the front-end block of the Class-A power amplifier followed by the back-end block of the Class-A power amplifier. The biasing-current switching-network dynamically sets the back-end block biasing current of the Class-A power amplifier for a highest possible operating efficiency. The gain-control network simultaneously adjusts gain of the front-end block of the Class-A power amplifier to synchronize with a dynamic-biasing current-switching configuration to allow overall gain of the Class-A power amplifier to be constant in all biasing conditions.

Mmic Dc-To-Dc Converter

US Patent:
2006008, Apr 27, 2006
Filed:
Dec 8, 2005
Appl. No.:
11/298087
Inventors:
Norman Scheinberg - South River NJ, US
Assignee:
Anadigics, Inc. - Warren NJ
International Classification:
G05F 1/40
US Classification:
323282000
Abstract:
An improved Monolithic Microwave Integrated Circuit DC-to-DC voltage converter fabricated in GaAs MESFET technology is introduced. The converter comprises a differential oscillator having crossed-coupled symmetrical inductors that ensure low-noise operation. The converter further comprises a highly-efficient synchronous rectifier and a start-up circuit.

Jfet Current Mirror And Voltage Level Shifting Apparatus

US Patent:
4743862, May 10, 1988
Filed:
May 2, 1986
Appl. No.:
6/858797
Inventors:
Norman R. Scheinberg - South River NJ
Assignee:
Anadigics, Inc. - Warren NJ
International Classification:
H03F 316
US Classification:
330277
Abstract:
A JFET current mirror is employed in the voltage level shifting section of an operational amplifier. The JFET current mirror includes a first and second JFET coupled at their gates for conducting current I1 and I2 respectively. The gate of a third JFET is connected to the drain of the first JFET and the source of the third JFET is connected by a plurality of diodes to the gate of the first JFET. Current flowing through the diodes produces a voltage drop across the diodes sufficient to bias the first JFET into saturation so that I2 will track I1. A fixed resistance R in the path of I2 produces a predetermined voltage level shift provided that I1 is constant. Therefore, a voltage applied to one terminal of R is level shifted by a predetermined voltage with respect to the other terminal of R. The voltage shifted output is then coupled to an internal amplifier section and the output buffer section of the operational amplifier.

Adjustable Low Spurious Signal Dc-Dc Converter

US Patent:
6314008, Nov 6, 2001
Filed:
Oct 16, 2000
Appl. No.:
9/688548
Inventors:
Jianwen Bao - Bethlehem PA
John van Saders - Asbury NJ
Norman Scheinberg - South River NJ
International Classification:
H02M 114
US Classification:
363 44
Abstract:
The present invention uses an AC signal and an external DC control voltage to generate a plurality of levels of output DC voltages. The level of the output voltage is determined by the DC control voltage and has the opposite polarity. The invention is preferably implemented as a balanced circuit, which generates spurious signals at even harmonics of the AC frequency signal. The spurious signals can then be filtered out using a low-pass filter.

Low Cost Monolithic Gallium Arsenide Upconverter Chip

US Patent:
5625307, Apr 29, 1997
Filed:
Mar 3, 1992
Appl. No.:
7/845293
Inventors:
Norman R. Scheinberg - South River NJ
Assignee:
Anadigics, Inc. - Warren NJ
International Classification:
H03B 1900
H01L 2500
H04B 128
US Classification:
327113
Abstract:
A monolithic upconverter integrated circuit is described which performs the first frequency conversion of a dual conversion cable television (CATV) receiver. The upconverter chip includes three functional blocks: a Gilbert type image-rejecting mixer, a phase splitter, and a voltage-controlled oscillator. Mixing is performed by a novel Gilbert type mixer including image-rejection inductors to improve the noise figure of the mixer. A differential circuit topology allows the monolithic upconverter chip to utilize a plastic dual inline batwing package without considerable performance loss. On-chip RF bypass networks, in the form of series RC terminations, also help compensate for the undesirable effects of pin inductances in the dual inline package. A resistor-based DC biasing scheme dramatically reduces power-up latency, allowing faster testing.

Low Cost Monolithic Gaas Upconverter Chip

US Patent:
5563545, Oct 8, 1996
Filed:
Sep 27, 1994
Appl. No.:
8/312730
Inventors:
Norman R. Scheinberg - South River NJ
Assignee:
Anadigics, Inc. - Warren NJ
International Classification:
H03K 1716
H03K 17687
US Classification:
327389
Abstract:
A monolithic upconverter integrated circuit is described which performs the first frequency conversion of a dual conversion cable television (CATV) receiver. The upconverter chip includes three functional blocks: a Gilbert type image-rejecting mixer, a phase splitter, and a voltage-controlled oscillator. Mixing is performed by a novel Gilbert type mixer including image-rejection inductors to improve the noise figure of the mixer. A differential circuit topology allows the monolithic upconverter chip to utilize a plastic dual inline batwing package without considerable performance loss. On-chip RF bypass networks, in the form of series RC terminations, also help compensate for the undesirable effects of pin inductances in the dual inline package. A resistor-based DC biasing scheme dramatically reduces power-up latency, allowing faster testing.

Current Bleeder Amplifier With Positive Feedback

US Patent:
4739282, Apr 19, 1988
Filed:
Jul 21, 1986
Appl. No.:
6/887217
Inventors:
Norman R. Scheinberg - South River NJ
Assignee:
Anadigics, Inc. - Warren NJ
International Classification:
H03F 316
H03F 138
US Classification:
330277
Abstract:
An FET amplifier having a current bleeder includes a positive feedback path for increasing the overall gain of the device. The positive feedback path includes an additional FET having its drain source path connected to the current bleeder and its gate connected to the output of the amplifier. The positive feedback causes the current through the current bleeder to vary in direct response to the output of the amplifier, thereby significantly increasing its overall gain.

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