Norris J Krone, 937410 Georgetown Ct, Mc Lean, VA 22102
Norris Krone Phones & Addresses
7410 Georgetown Ct, McLean, VA 22102 703-8480331
Mc Lean, VA
Lusby, MD
Kitty Hawk, NC
Annandale, VA
Work
Position:
Professional/Technical
Education
Degree:
High school graduate or higher
Mentions for Norris J Krone
Publications & IP owners
Us Patents
Linear Array Sensors For Target Detection Including Hydrocarbon Events Such As Gun, Mortar, Rpg Missile And Artillery Firings
US Patent:
7880870, Feb 1, 2011
Filed:
Oct 5, 2006
Appl. No.:
11/543261
Inventors:
Mehmet Can Ertem - Bethesda MD, US
Eric Heidhausen - Woodbine MD, US
Norris J. Krone - McLean VA, US
Eric Heidhausen - Woodbine MD, US
Norris J. Krone - McLean VA, US
Assignee:
University Research Foundation, Inc. - Greenbelt MD
International Classification:
G01B 11/26
US Classification:
35613904, 35613901, 35613902, 35613903, 244 314, 2502036
Abstract:
Detection sensors utilizing linear arrays using one or more linear arrays of detectors sampled at a high rate. The invention is useful for target detection including hydrocarbon events such as guns, mortars, RPG missiles and artillery firings, lightning, and other optical events.
Ultra High Speed Data Collection, Processing And Distriubtion Ring With Parallel Data Paths Between Nodes
US Patent:
5841974, Nov 24, 1998
Filed:
Mar 18, 1996
Appl. No.:
8/617051
Inventors:
Norris Krone - Annandale VA
Roger Pierson - Castleton VA
Glenn Connor - Laurel MD
Virgil Davis - Fulton MD
Roger Pierson - Castleton VA
Glenn Connor - Laurel MD
Virgil Davis - Fulton MD
Assignee:
University Research Foundation, Inc. - Greenbelt MD
International Classification:
G06F 1338
H04J 302
H04J 302
US Classification:
39520031
Abstract:
A high speed data collection processing and distribution system for coupling a plurality of digital data sources to a plurality of digital data processors. The system includes a plurality of segmented parallel data paths and a plurality of nodes connecting said parallel data paths in an endless ring. Each node includes an input connector for connecting the end of one of said segments of parallel data paths on a one-for-one basis; a data multiplexer, a plurality of node parallel data paths in the node corresponding to the segmented parallel data paths, respectively, connected to the input connector and the data multiplexer such that data input to the multiplexer corresponds to respective ones of the segmented parallel data paths. A processor is coupled to said node parallel data paths, and as a second input to the multiplexer a common source of clock and slot signals is independently connected to said control processor in each node, respectively, for controlling the timing thereof. Each node also includes transmit and receive FIFO buffer memories, address, exclusive source and pattern match circuits and a local clock distribution circuit.
Ultra High Speed Data Collection, Processing And Distribution Ring With Parallel Data Paths Between Nodes
US Patent:
5502817, Mar 26, 1996
Filed:
Apr 2, 1993
Appl. No.:
8/042273
Inventors:
Norris Krone - Annandale VA
Roger Pierson - Castleton VA
Glenn Connor - Laurel MD
Virgil Davis - Fulton MD
Roger Pierson - Castleton VA
Glenn Connor - Laurel MD
Virgil Davis - Fulton MD
Assignee:
University Research Foundation, Inc. - Greenbelt MD
International Classification:
G06F 1338
H04J 302
H04J 302
US Classification:
39520016
Abstract:
A high speed data collection processing and distribution system for coupling a plurality of digital data sources to a plurality of digital data processors. The system includes a plurality of segmented parallel data paths and a plurality of nodes connecting said parallel data paths in an endless ring. Each node includes an input connector for connecting the end of one of said segments of parallel data paths on a one-for-one basis; a data multiplexer, a plurality of node parallel data paths in the node corresponding to the segmented parallel data paths, respectively, connected to the input connector and the data multiplexer such that data input to the multiplexer corresponds to respective ones of the segmented parallel data paths. A processor is coupled to said node parallel data paths, and as a second input to the multiplexer a common source of clock and slot signals is independently connected to said control processor in each node, respectively, for controlling the timing thereof. Each node also includes transmit and receive FIFO buffer memories, address, exclusive source and pattern match circuits and a local clock distribution circuit.
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