Pamela S Trammel, 671325 Cordelia Ave, San Jose, CA 95129

6399462, Jun 4, 2002

Jun 30, 1997

08/885046

Krishnaswamy Ramkumar - San Jose CA
Sang S. Kim - Laguna Hills CA
Sharmin Sadoughi - Cupertino CA
Pamela Trammel - San Jose CA
Avner Shelem - San Jose CA

Cypress Semiconductor Corporation - San Jose CA

H01L 2176

438439, 438297, 438424, 438425

A method of forming a field oxide or isolation region in a semiconductor die. A nitride layer (over an oxide layer disposed over a substrate) is patterned and subsequently etched so that the nitride layer has a nearly vertical sidewall. The oxide layer and the substrate in the isolation region are etched to form a recess in the substrate having a sloped surface with respect to the nearly vertical sidewall of the nitride layer. A field oxide is then grown in the recess using a high pressure, dry oxidizing atmosphere. The sloped sidewall of the substrate effectively moves the face of the exposed substrate away from the edge of the nitride layer sidewall. Compared to non-sloped techniques, the oxidation appears to start with a built-in offset from the patterned etch. This leads to a reduction of oxide encroachment and a nearly non-existent birds beak. The desirable range of slopes for the substrate sidewall is approximately 50Â-80Â with respect to a nearly planar surface of the substrate in the recess.

6579777, Jun 17, 2003

Jan 16, 1996

08/587417

Ting P. Yen - Fremont CA
Pamela S. Trammel - San Jose CA
Philippe Schoenborn - San Jose CA
Alexander H. Owens - Los Gatos CA

Cypress Semiconductor Corp. - San Jose CA
LSI Logic Corporation - Milpitas CA

H01L 2176

438444, 438296, 438297, 438359, 438362, 438425

A method of forming a localized oxidation having reduced birds beak encroachment in a semiconductor device by providing an opening in the silicon substrate that has sloped sidewalls with a taper between about 10Â and about 75Â as measured from the vertical axis of the recess opening and then growing field oxide within the tapered recess opening for forming the localized oxidation.

6704487, Mar 9, 2004

Aug 10, 2001

09/927256

Farnaz Parhami - Fremont CA
Alice Liu - San Jose CA
Pamela S. Trammel - San Jose CA

Lightwave Microsystems Corporation - San Jose CA

G02B 610

385129

A method of making an optical waveguide structure for an active PLC device having a reduced dn/dt birefringence. The method includes the step of forming a waveguide core layer on a bottom cladding, the waveguide core layer having a higher refractive index than the bottom cladding. The waveguide core layer is then etched to define a waveguide core. A top cladding is subsequently formed over the waveguide core and the bottom cladding. The top cladding also has a lower refractive index than the waveguide core. The top cladding is then etched to define a first trench and a second trench parallel to the waveguide core. The first trench and the second trench are configured to relieve a stress on the waveguide core. This stress can be induced by a heater, as in a case where the active PLC is a thermo-optic PLC. The first trench and the second trench can extend from an upper surface of the top cladding to an upper surface of the bottom cladding.

6709882, Mar 23, 2004

Aug 27, 2001

09/940567

Pamela S. Trammel - San Jose CA
Jonathan G. Bornstein - Cupertino CA
David H. Menche - Redwood City CA

Lightwave Microsystems Corporation - San Jose CA

H01L 2100

438 29, 438 31, 438618, 438689, 385129, 385130, 385131

A method for making a resistive heater for a planar lightwave circuit. The method includes the step of depositing a resistive layer on a top clad of a planar lightwave circuit. An interconnect layer is subsequently deposited over the resistive layer. The resistive layer can be tungsten and the interconnect layer can be aluminum. The interconnect layer is then etched to define a heater interconnect, wherein the heater interconnect is disposed over the resistive layer and has a first width. The heater interconnect is then masked, and the resistive layer is etched to define a resistive heater. The resistive heater is disposed beneath the heater interconnect and has a second width larger than the first width. The heater interconnect is defined to include a heater conduct region between a first contact pad and a second contact pad such that a current between the first contact pad and the second contact pad is conducted through the resistive heater, thereby generating heat which is conducted into the top clad of the planar lightwave circuit. The difference between the first width of the heater interconnect and the larger second width of the underlying resistive heater is determined to decrease an alignment sensitivity of a lithography process for masking the heater interconnect.

7421156, Sep 2, 2008

Feb 9, 2006

11/351031

Alice Liu - San Jose CA, US
Pamela Shiell Trammel - San Jose CA, US

Lightwave Microsystems Corporation - San Jose CA

G02B 6/12
G02B 6/00

385 14, 385 11, 385 15

Polarization dependent loss may be reduced by providing at least one dummy waveguide or at least one dummy metal structure. Polarization dependent loss may also be reduced by imposing a mechanical force on the OIC to exert mechanical stress thereby changing at least one of the birefringence and the optical axes of at least one waveguide. And polarization dependent loss may be reduced by forming a metal heater using a first set of metal deposition parameters; forming a conductive metal structure contacting the metal heater using a second set of metal deposition parameters; and selecting the first set of metal deposition parameters and the second set of metal deposition parameters to reduce stress.

7577324, Aug 18, 2009

Jul 29, 2008

12/181905

Alice Liu - San Jose CA, US
Pamela Shiell Trammel - San Jose CA, US

NeoPhotonics Corporation - San Jose CA

G02B 6/12
G02B 6/00

385 14, 385 4, 385 11, 385 15

Polarization dependent loss may be reduced by providing at least one dummy waveguide or at least one dummy metal structure. Polarization dependent loss may also be reduced by imposing a mechanical force on the OIC to exert mechanical stress thereby changing at least one of the birefringence and the optical axes of at least one waveguide. And polarization dependent loss may be reduced by forming a metal heater using a first set of metal deposition parameters; forming a conductive metal structure contacting the metal heater using a second set of metal deposition parameters; and selecting the first set of metal deposition parameters and the second set of metal deposition parameters to reduce stress.

2003000, Jan 2, 2003

Jun 29, 2001

09/895341

Nizar Kheraj - San Jose CA, US
Pamela Trammel - San Jose CA, US
Fan Zhong - Fremont CA, US
Jonathan Bornstein - Cupertino CA, US

G02B006/00

216/024000

In a planar lightwave circuit, a method of making an optical waveguide that resists core deformation. The method includes a step of forming a core layer on a bottom clad. A waveguide core is formed from the core layer using an etching process. The waveguide core is fabricated to have a higher refractive index than the bottom clad. A silica glass cap layer is then formed over the waveguide core and the bottom clad. A top clad is then formed over the waveguide core, the silica glass cap layer, and the bottom clad. The waveguide core has a higher refractive index than the top clad. The silica glass cap layer maintains the shape of the waveguide core during an anneal process of the top clad. The silica glass cap layer can be deposited using PECVD (plasma enhanced chemical vapor deposition). The silica glass cap layer can be between 0.3 to 2 microns thick. The silica glass cap layer can be undoped silica glass. The silica glass cap layer can have a higher reflow temperature than the waveguide core to prevent deformation of the waveguide core. The silica glass cap layer also can prevent diffusion of dopant between the waveguide core and the top clad.

5468342, Nov 21, 1995

Apr 28, 1994

8/234478

James E. Nulty - San Jose CA
Pamela S. Trammel - San Jose CA

Cypress Semiconductor Corp. - San Jose CA

H01L 21306
C03C 1500
B44C 122

1566431

A method of etching openings in oxide layers is disclosed. A hard mask layer is formed on the oxide layer. The hard mask layer is then patterned by a photoresist layer and an etch is performed to form openings in the hard mask. Next, the patterning layer may be removed and an etch is performed to remove the oxide in the regions defined by the hard mask layer openings. The etch with hard mask has minimized aspect ratio dependency, so that openings of different sizes may be formed simultaneously. An etch that may be carried out with Freon 134a (C. sub. 2 H. sub. 2 F. sub. 4) to provide superior oxide:nitride selectivity is also disclosed. Additionally, the etch may be carried out at high temperature for improved wall profile without loss of selectivity. For deep openings, a two step etch process is disclosed, with a polymer clean step between the etches to remove polymer build up from first etch, and allow the etch to proceed to an increased depth.