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Pankaj Gupta, 54San Ramon, CA

Pankaj Gupta Phones & Addresses

San Ramon, CA   

Boone, NC   

300 Broad St, Stamford, CT 06901    203-9610614   

300 Broad St #302, Stamford, CT 06901    203-9610614   

New York, NY   

Watauga, NC   

Mentions for Pankaj Gupta

Pankaj Gupta resumes & CV records

Resumes

Pankaj Gupta Photo 31

Pankaj (Pk) Gupta - Piscataway, NJ

Work:
Veeco Instruments Mar 2014 to 2000
Services Marketing Manager
Mera Medicare Dec 2012 to 2000
Founder & Adviser
Toshiba International Corporation - Houston, TX Sep 2012 to Mar 2014
Product Manager
Mera Medicare Nov 2010 to Dec 2012
Founder
Luminus Devices - Billerica, MA Mar 2011 to Sep 2012
Product Marketing Manager
LED Wave - New York, NY Oct 2010 to Feb 2011
Business Development Intern
Laboratory of Laser Energetics Dec 2008 to Jul 2010
Research Assistant
Supergems Jewelry Mfg. Pvt. Ltd Jul 2006 to Jul 2008
R&D Manager
Education:
University of Maryland Jan 2011
Entrepreneurship
University of Rochester May 2010
MS in Optics
Visvesvaraya National Institute of Technology Apr 2006
BS in Engineering
Indian Institute of Technology Roorkee Dec 2005 University of Stanford
Business Management Studies
University of Virginia Darden School of Business
Business Strategy
Wharton School at University of Pennsylvania
Marketing
Pankaj Gupta Photo 32

Pankaj Gupta - Little Ferry, NJ

Work:
Immunomedics Inc - Morris Plains, NJ Mar 2008 to Jul 2012
Assistant Director
Columbia University Medical Center - New York, NY Jul 2003 to Feb 2008
Associate Research Scientist
Columbia University, Dept of Biological Sciences - New York, NY Jan 2000 to Jul 2003
Post-doctoral Research Scientist
Jawaharlal Nehru University - New Delhi, Delhi Jul 1994 to Dec 1999
Graduate Student
Education:
Jawaharlal Nehru University - New Delhi, Delhi 1999
Ph. D in Biotechnology
Pankaj Gupta Photo 33

Pankaj Gupta

Work:
HCL Axon Sep 2011 to 2000
SAP BW Sr. Project Manager
HCL Axon Mar 2006 to Sep 2011
SAP BW Manager / Lead
HCL Technologies Jan 2005 to Mar 2006
BW data conversion lead
HCL Technologies Jun 2004 to Jan 2005
Project lead
HCL Technologies Jun 2002 to Jun 2004
Sr. Software Engineer
HCL Technologies - Hong Kong, Hong Kong Island Jun 2001 to Jun 2002
Sr. Software Engineer
HCL Technologies Mar 2000 to Jun 2001
Sr. Software Engineer
Softek Ltd Sep 1999 to Mar 2000
Software Engineer
NIIT Ltd Sep 1998 to May 1999
Software Engineer

Publications & IP owners

Us Patents

High-Speed Message Forwarding Lookups For Arbitrary Length Strings Using Pipelined Memories

US Patent:
7017021, Mar 21, 2006
Filed:
Apr 4, 2001
Appl. No.:
09/827270
Inventors:
Pankaj Gupta - Mountain View CA, US
Srinivasan Venkatachary - Sunnyvale CA, US
Assignee:
Cypress Semiconductor Corp. - San Jose CA
International Classification:
G06F 12/00
US Classification:
711169
Abstract:
The invention provides a method and system for lookup of message header information that has the advantages of low-power, speed, and flexibility. The invention uses a sequence of pipelined on-chip memories, each having only a portion of the header information intended for lookup. Each one of the on-chip memories simultaneously performs a lookup on a portion of the header information, allowing embodiments of the invention to operate on multiple messages worth of header information substantially simultaneously. The invention uses a novel data structure for recording destination addresses in the sequence of on-chip memories, having the property that moving information about destination addresses, or otherwise responding to changes in network topology is flexible, while at the same time maintaining relatively dense usage of the on-chip memories. The novel data structure allows embodiments of the invention to find the longest match destination address with no substantial additional processing over random-access memory lookup.

Method For On-The-Fly Error Correction In A Content Addressable Memory (Cam) And Device Therefor

US Patent:
7304873, Dec 4, 2007
Filed:
Jan 25, 2005
Appl. No.:
11/043391
Inventors:
Pankaj Gupta - Palo Alto CA, US
Assignee:
Netlogic Microsystems, Inc. - Mountain View CA
International Classification:
G11C 15/00
US Classification:
365 49, 36518907, 711200
Abstract:
A CAM system () can include a number of entries (- to -) having one portion for storing a data value (e. g. , E) and another portion for storing a replicated data value (E(REP)). For on-the-fly error correction, the entries can be searched by applying an appended key value that includes a key portion (KEY) and replicated key portion (KEY(REP)).

System And Method For Efficiently Searching A Forwarding Database That Is Split Into A Bounded Number Of Sub-Databases Having A Bounded Size

US Patent:
7426518, Sep 16, 2008
Filed:
Mar 28, 2003
Appl. No.:
10/402887
Inventors:
Srinivasan Venkatachary - Sunnyvale CA, US
Pankaj Gupta - Mountain View CA, US
Assignee:
NetLogic Microsystems, Inc. - Mountain View CA
International Classification:
G06F 17/30
US Classification:
707101, 707102
Abstract:
A method, apparatus, and storage medium product are provided for forming a forwarding database, and for using the formed database to more efficiently and quickly route packets of data across a computer network. The forwarding database is arranged into multiple sub-databases. Each sub-database is pointed to by a pointer within a pointer table. When performing a longest-match search of incoming addresses, a longest prefix matching algorithm can be used to find the longest match among specialized “spear prefixes” stored in the pointer table. After the longest spear prefixes are found, the pointer table will direct the next search within a sub-database pointed to by that spear prefix. Another longest-match search can be performed for database prefixes (or simply “prefixes”) within the sub-database selected by the pointer. Only the sub-database of interest will, therefore, be searched and all other sub-databases are not accessed. Using a precursor pointer and a sub-database of optimally bounded size and number ensures power consumption be confined only to the sub-database being accessed, and that higher speed lookup operations can be achieved since only the sub-database of interest is being searched.

Architecture For Network Search Engines With Fixed Latency, High Capacity, And High Throughput

US Patent:
7437354, Oct 14, 2008
Filed:
May 7, 2004
Appl. No.:
10/841607
Inventors:
Srinivasan Venkatachary - Sunnyvale CA, US
Pankaj Gupta - Palo Alto CA, US
Anand Rangarajan - Sunnyvale CA, US
Assignee:
NetLogic Microsystems, Inc. - Mountain View CA
International Classification:
G06F 17/30
US Classification:
707 3, 707204, 707 1, 707 2
Abstract:
An improved architecture for a network search engine (NSE) is disclosed herein as including an interface manager, one or more levels of a splitting engine, an array of data processing units (DPUs), and a cascade block. A method for using the improved NSE architecture to form an efficient pointer entry database is also provided. As described herein, the improved NSE architecture simultaneously provides high speed, search throughput, update rate and capacity, coupled with low power and fixed latency searches for all search key widths.

Network Device, Storage Medium And Methods For Incrementally Updating A Forwarding Database

US Patent:
7571156, Aug 4, 2009
Filed:
Mar 25, 2004
Appl. No.:
10/809244
Inventors:
Pankaj Gupta - Palo Alto CA, US
Srinivasan Venkatachary - Sunnyvale CA, US
Assignee:
NetLogic Microsystems, Inc. - Mountain View CA
International Classification:
G06F 7/00
G06F 17/30
US Classification:
707 3, 707101, 707102
Abstract:
Network devices, storage mediums and methods for updating a memory structure in a data plane of the network device when route updates are received in the control plane of the network device. The methods described herein can be used to perform one of the following algorithms: a Basic Incremental Split-Merge (BISM) algorithm, a Lazy Incremental Split-Merge (LISM) algorithm, and a Down-support Split-Merge (DSM) algorithm. Each of the algorithms described herein may be used to incrementally update portions of a forwarding database stored within the memory structure, where the updated portions correspond to only those portions affected by the route updates.

Method And Apparatus For Constructing A Failure Tree From A Search Tree

US Patent:
7610269, Oct 27, 2009
Filed:
Jul 30, 2007
Appl. No.:
11/830360
Inventors:
Pankaj Gupta - Palo Alto CA, US
Srinivasan Venkatachary - Sunnyvale CA, US
Assignee:
NetLogic Microsystems, Inc. - Mountain View CA
International Classification:
G06F 17/30
US Classification:
707 2, 707100
Abstract:
A method for representing a search tree embodying a plurality of signatures to be searched for in an input string of characters constructs a failure tree in which the states are re-organized in levels according to the number of failure transitions between each state and the root node of the search tree.

Network Search Engine (Nse) And Method For Performing Interval Location Using Prefix Matching

US Patent:
7624226, Nov 24, 2009
Filed:
Dec 20, 2006
Appl. No.:
11/614075
Inventors:
Srinivasan Venkatachary - Sunnyvale CA, US
Pankaj Gupta - Palo Alto CA, US
Assignee:
NetLogic Microsystems, Inc. - Mountain View CA
International Classification:
G06F 13/10
US Classification:
711108
Abstract:
A communication network, networking device and method is provided herein for locating (i. e. , searching for) an interval of numbers i within a set of numbers N given a point P. The search algorithm provided herein provides fast search speed (e. g. , requires only one memory access) with minimum storage requirements (e. g. , consumes up to, but not exceeding, N entries within a memory device).

Method And Apparatus For Optimizing String Search Operations

US Patent:
7636717, Dec 22, 2009
Filed:
Mar 21, 2007
Appl. No.:
11/689421
Inventors:
Pankaj Gupta - Palo Alto CA, US
Srinivasan Venkatachary - Sunnyvale CA, US
Assignee:
NetLogic Microsystems, Inc. - Mountain View CA
International Classification:
G06F 17/30
G06F 17/00
US Classification:
707 6, 707 2, 707101
Abstract:
A search tree embodying a plurality of signatures to be compared with an input string of characters and including a number of success transitions characterized by a success size parameter and including a number of failure transitions characterized by a failure size parameter is selectively modified to achieve a desired balance between processing speed and memory area requirements.

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