Patrick Caraher resumes & CV records
Resumes
Patrick Thomas Caraher, 536816 Audubon Ave, Longmont, CO 80503
Patrick Caraher Phones & Addresses
6816 Audubon Ave, Longmont, CO 80503 503-6457513
Niwot, CO
3850 172Nd Ave, Beaverton, OR 97006 503-6457513
2364 Division St, Portland, OR 97202
12570 Portland Ave, Burnsville, MN 55337 952-7071905
Novi, MI
Beverly Hills, MI
East Lansing, MI
3850 NW 172Nd Pl, Beaverton, OR 97006
Social networks
Patrick Thomas Caraher
Linkedin
Work
Position:
Professional/Technical
Education
Degree:
Associate degree or higher
Mentions for Patrick Thomas Caraher
Publications & IP owners
Us Patents
Intelligent Memory Device Test Rack
US Patent:
2022023, Jul 21, 2022
Filed:
Apr 8, 2022
Appl. No.:
17/716972
Inventors:
- Boise ID, US
Michael R. Spica - Eagle ID, US
Donald Shepard - Longmont CO, US
Patrick Caraher - Longmont CO, US
João Elmiro da Rocha Chaves - Middleton ID, US
Michael R. Spica - Eagle ID, US
Donald Shepard - Longmont CO, US
Patrick Caraher - Longmont CO, US
João Elmiro da Rocha Chaves - Middleton ID, US
International Classification:
G11C 29/44
G11C 29/56
G11C 29/36
G06F 9/50
G11C 29/22
G11C 29/56
G11C 29/36
G06F 9/50
G11C 29/22
Abstract:
A detection is made by a processing device allocated to a memory device test board of a distributed test platform that a memory sub-system has engaged with a memory device test resource of the memory device test board. A test is identified to be performed for a memory device of the memory sub-system. The test includes first instructions to be executed by a memory sub-system controller of the memory sub-system in performance of the test and second instructions to be executed by the processing device in performance of the test. The second instructions are to cause one or more test condition components of the memory device test resource to generate one or more test conditions to be applied to the memory device while the memory sub-system executes the first instructions. Responsive to a transmission of the first instructions to the memory sub-system controller, the second instructions are executed.
Power Management Component For Memory Sub-System Voltage Regulation
US Patent:
2023002, Jan 26, 2023
Filed:
Oct 7, 2022
Appl. No.:
17/961999
Inventors:
- Boise ID, US
Patrick T. Caraher - Niwot CO, US
Patrick T. Caraher - Niwot CO, US
International Classification:
G06F 11/07
G06F 11/30
G06F 11/30
Abstract:
A memory sub-system comprises a power management component comprising a plurality of regulators configured to supply respective operating voltages for components of the memory sub-system. The power management component is configured to adjust a regulator voltage level provided to a particular component until an operation state change of the particular component is detected. The power management voltage level is further configured to determine a value of the regulator voltage level at which the operation state change of the particular component is detected.
Power Management Component For Memory Sub-System Voltage Regulation
US Patent:
2021022, Jul 22, 2021
Filed:
Apr 2, 2021
Appl. No.:
17/221065
Inventors:
- Boise ID, US
Patrick T. Caraher - Niwot CO, US
Patrick T. Caraher - Niwot CO, US
International Classification:
G06F 11/07
G06F 11/30
G06F 11/30
Abstract:
A memory sub-system comprises a power management component comprising a plurality of regulators configured to supply respective operating voltages for components of the memory sub-system. The power management component is configured to adjust a regulator voltage level provided to a particular component until an operation state change of the particular component is detected. The power management voltage level is further configured to determine a value of the regulator voltage level at which the operation state change of the particular component is detected.
Power Management Component For Memory Sub-System Voltage Regulation
US Patent:
2020024, Jul 30, 2020
Filed:
Jan 30, 2019
Appl. No.:
16/262111
Inventors:
- Boise ID, US
Patrick T. Caraher - Niwot CO, US
Patrick T. Caraher - Niwot CO, US
International Classification:
G11C 5/14
G06F 11/07
G01R 19/165
G06F 11/07
G01R 19/165
Abstract:
A memory sub-system comprises a power management component comprising a plurality of regulators configured to supply respective operating voltages for components of the memory sub-system. The power management component is configured to adjust a regulator voltage level provided to a particular component until an operation state change of the particular component is detected. The power management voltage level is further configured to determine a value of the regulator voltage level at which the operation state change of the particular component is detected.
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