Patrick A O'Malley, 45185 E Campina Dr, Litchfield Park, AZ 85340

6895596, May 17, 2005

Dec 23, 1997

08/997622

William E. Salzer - Gilbert AZ, US
Mary E. Gallagher - Phoenix AZ, US
Patrick J. O'Malley - Chandler AZ, US

Freescale Semiconductor, Inc. - Austin TX

H04N007/16

725142, 725139, 725151, 386 97, 386 99, 370537, 348481, 348485

A circuit and method of interleaving a data stream (DATA) in which the data to be interleaved is contained in separate sections of the data stream. A buffer storage circuit () receives and stores the data stream. A first section (T-T) of the data stream is transferred to a first memory circuit () and a second section (T-T) of the data stream is transferred to a second memory circuit (). A multiplexer circuit () receives data from the first and second memory circuits and selects between the first and second sections of the data stream in response to a selection signal to produce an interleaved output signal.

4670745, Jun 2, 1987

Nov 15, 1983

6/551811

Patrick J. O'Malley - Chandler AZ
William M. Peterson - Tempe AZ

Motorola Inc. - Schaumburg IL

G09G 116

340801

A video raster display system having a dedicated display address generator is provided. In addition to a microprocessor contained within the video display system providing addresses to a memory the display address generator also generates addresses. The display address generator has a logic unit having a first and a second bus as inputs. A first plurality of registers, some of which are controllably coupled to said first bus and some of which are controllably coupled to said second bus, receives inputs from the microprocessor. A second plurality of registers, some of which are controllably coupled to said first bus and some of which are controllably coupled to said second bus, receives inputs from a video data generator. A third plurality of registers, some of which are controllably coupled to said first bus and some of which are controllably coupled to said second bus, receives the output from the logic unit to controllably provide this output to the logic unit for subsequent operations.

5594437, Jan 14, 1997

Aug 1, 1994

8/283350

Patrick J. O'Malley - Chandler AZ

Motorola, Inc. - Schaumburg IL

G06F 720

341 67

A bit stream unpacking circuit (10) parses data fields from a serial bitstream as an initial step in decompression. The protocol of the incoming packed data stream is stored in a control ROM (24). As each packed data field arrives, the control ROM provides size and condition instructions (18) to parse out the fields from the serial data stream and store the fields in data storage (14) for later retrieval. The size instruction determines the length of the field in the incoming data. A counter (26) counts clock signals of the incoming serial bitstream and matches the count with the size instruction to determine when a data field has arrived. The condition instruction determines the next address in the control ROM based on the incoming bitstream. Once the incoming message has been parse out and stored, the individual data field may be read directly from the data storage for decompression.

4626839, Dec 2, 1986

Nov 15, 1983

6/551812

Patrick J. O'Malley - Chandler AZ

Motorola Inc. - Schuamburg IL

G09G 114

340750

A video display system is provided having a programmable video display generator. The video display generator is divided into a control unit and an interface unit. The control unit has a dedicated display address generator which frees up the microprocessor used in the video display system. The system is capable of operation with several different microprocessors as well as with different types of random access memories. Circuitry within the interface unit advises the system of the type of microprocessor being used as well as the type of random access memory. The interface unit controls character generation as well as final attribute circuitry which gives the video display generator a high degree of capability while minimizing the amount of circuitry required.