Paul M Goodwin, 3721 Linden St, Somersworth, NH 03878

6353876, Mar 5, 2002

Aug 22, 2000

09/643431

Paul M. Goodwin - Littleton MA
Stephen Van Doren - Northborough MA

Compaq Information Technologies Group, L.P. - Houston TX

G06F 1208

711143, 711121, 711133, 711148, 711153, 710132

Data coherency in a multiprocessor system is improved and data latency minimized through the use of data mapping âfillâ requests from any one of the multiprocessor CPUs such that the information requested is acquired through the crossbar switch from the same memory module to which the âvictimâ data in that CPUs cache must be rewritten. With such an arrangement rewrite latency periods for victim data within the crossbar switch is minimized and the ships crossing in the night problem is avoided.

7779811, Aug 24, 2010

Sep 13, 2006

11/520214

William James Mailander - Beverly MA, US
Paul Bryant Goodwin - Hamilton OH, US

General Electric Company - Schenectady NY

F02C 9/28
G05B 9/03

123399, 60782

A gas turbine engine control component includes at least one electronic device, electronics such as an integrated circuit associated with the device, and a thermoelectric cooler for cooling the electronics mounted in a compartment. The thermoelectric cooler may be disposed in or on a wall of the compartment with a heat sink connected to a hot side of the thermoelectric cooler and a cold side of the thermoelectric cooler exposed to an interior of the compartment. Data about and/or operating instructions for the device may be stored in memory on the integrated circuit. The data may be calibration information for the device. A bus connector is connected to the integrated circuit for transferring operating instructions and/or data from the integrated circuit out and/or out of the component. A controller or control system incorporating these devices and components have the devices electronically connected to the integrated circuit.

8237786, Aug 7, 2012

Mar 31, 2010

12/751816

Gaudenz Danuser - Cambridge MA, US
Paul C. Goodwin - Shoreline WA, US

Applied Precision, Inc. - Issaquah WA

H04N 9/47
H04N 13/04

348 79

Embodiments of the present invention are directed to imaging technologies, and, in particular, to an imaging system that detects relatively weak signals, over time, and that uses the detected signals to determine the positions of signal emitters. Particular embodiments of the present invention are directed to methods and systems for imaging fluorophore-labeled samples in order to produce images of the sample at resolutions significantly greater than the diffraction-limited resolution associated with optical microscopy. Embodiments of the present invention employ overlapping-emitter-image disambiguation to allow data to be collected from densely arranged emitters, which significantly decreases the data-collection time for producing intermediate images as well as the number of intermediate images needed to computationally construct high-resolution final images. Additional embodiments of the present invention employ hierarchical image-processing techniques to further resolve and interpret disambiguated images.

2012026, Oct 25, 2012

Jun 28, 2012

13/535468

GAUDENZ DANUSER - CAMBRIDGE MA, US
PAUL C. GOODWIN - SHORELINE WA, US

APPLIED PRECISION, INC. - ISSAQUAH WA

H04N 7/18

348 79

Embodiments of the present invention are directed to imaging technologies, and, in particular, to an imaging system that detects relatively weak signals, over time, and that uses the detected signals to determine the positions of signal emitters. Particular embodiments of the present invention are directed to methods and systems for imaging fluorophore-labeled samples in order to produce images of the sample at resolutions significantly greater than the diffraction-limited resolution associated with optical microscopy. Embodiments of the present invention employ overlapping-emitter-image disambiguation to allow data to be collected from densely arranged emitters, which significantly decreases the data-collection time for producing intermediate images as well as the number of intermediate images needed to computationally construct high-resolution final images. Additional embodiments of the present invention employ hierarchical image-processing techniques to further resolve and interpret disambiguated images.

5461718, Oct 24, 1995

Apr 24, 1992

7/874076

David A. Tatosian - Stow MA
Paul M. Goodwin - Littleton MA
Donald Smelser - Bolton MA

Digital Equipment Corporation - Maynard MA

G06F 700
G06F 710
G06F 722

395416

A read buffering system employs a bank of FIFOs to hold sequential read data for a number of data streams being fetched by a computer. The FIFOs are located in the memory controller, so the system bus is not used in the memory accesses needed to fill the stream buffer. The buffer system stores addresses used for read requests made by a CPU, and if a next sequential address is then detected in a subsequent read request, this is designated to be a stream (i. e. , sequential reads). When a stream is thus detected, data is fetched from DRAM memory for addresses following the sequential address, and this prefetched data is stored in one of the FIFOs. A FIFO is selected using a least-recently-used algorithm. When the CPU subsequently makes a read request for data in a FIFO, this data can be returned without making a memory access, and so the access time seen by the CPU is shorter. By taking advantage of page mode, access to the DRAM memory for the prefetch operations can be transparent to the CPU, resulting in substantial performance improvement if sequential accesses are frequent.

6043987, Mar 28, 2000

Aug 25, 1997

8/918248

Paul M. Goodwin - Littleton MA
John Nerl - Londonderry NH

Compaq Computer Corporation - Houston TX

H05K 118

361763

Printed Circuit Board fabrication costs are decreased, and device placement densities are increased by the use of well structures designed for receiving components such as capacitors on portions of the PCB directly beneath integrated circuit packages having very low vertical profiles. With such an arrangement it is possible to use newer low profile packages and still place a capacitor under the integrated circuit package for reduced area consumption and improved inductance and circuit cycle times. Further advantages of the present arrangement include a reduction in the number of vias that need to be drilled in the PCB to make capacitor attachments, a consequent improvement in PCB inductance and parasitic capacitance, and improved electrical properties for voltage reference planes and routing layers.

5371870, Dec 6, 1994

Apr 24, 1992

7/874080

Paul M. Goodwin - Littleton MA
Donald Smelser - Bolton MA
David A. Tatosian - Stow MA

Digital Equipment Corporation - Maynard MA

G06F 1200
G06F 1300

395425

A read buffering system employs a bank of FIFOs to hold sequential read data for a number of data streams being fetched by a computer. The FIFOs are located in the memory controller, so the system bus is not used in the memory accesses needed to fill the stream buffer. The buffer system stores addresses used for read requests made by a CPU, and if a next sequential address is then detected in a subsequent read request, this is designated to be a stream (i. e. , sequential reads). When a stream is thus detected, data is fetched from DRAM memory for addresses following the sequential address, and this prefetched data is stored in one of the FIFOs. A FIFO is selected using a least-recently-used algorithm. When the CPU subsequently makes a read request for data in a FIFO, this data can be returned without making a memory access, and so the access time seen by the CPU is shorter. By taking advantage of page mode, access to the DRAM memory for the prefetch operations can be transparent to the CPU, resulting in substantial performance improvement if sequential accesses are frequent.

5216672, Jun 1, 1993

Apr 24, 1992

7/872976

David A. Tatosian - Stow MA
Donald W. Smelser - Bolton MA
Paul M. Goodwin - Littleton MA

Digital Equipment Corporation - Maynard MA

G06F 1126

371 211

A memory testing system for an electronic computing system includes multiple memory modules, each equipped with error detecting and correcting (EDC) circuitry, and is operable in a diagnostic test mode wherein read and write tests of the modules are performed in parallel. Each module includes a command/status register (CSR), used in identifying errors occurring in that module by capturing various signals at the time of the error. These signals include the type of error, the memory address involved in the error, the check bits of the data associated with the error, and the syndromes of the data. After pre-setting each CSR's diagnostic register, one module operates in a "target" mode, and the remaining modules operate in a "shadow" mode. The target module operates normally during read and write operations. When the target module is directed to write data to a particular address, the shadow modules write the same data to corresponding addresses in their memory banks.