Paul H Hohensee, 6815 Swart Ter, Nashua, NH 03064

6763452, Jul 13, 2004

Jun 24, 1999

09/339797

Paul H. Hohensee - Nashua NH
Korbin S. Van Dyke - Sunol CA
David L. Reese - Westborough MA
Stephen C. Purcell - Mountain View CA

ATI International SRL - Christ Church

G06F 900

712227, 712220, 703 22

A method and a multiprocessor computer for execution of the method. A first CPU has a general register file, an instruciton pipeline, and profile circuitry. The profile circuitry is operatively interconnected and under common hardware control with the instruction pipeline. The profile circuitry and instruction pipeline are cooperatively interconnected to detect the occurrence of profileable events occurring in the instruction pipeline. The profile circuitry is operable without software intervention to effect recording of profile information describing the profileable events into the general register file, without first capturing the information into a main memory of the computer. The recording is essentially concurrent with the occurrence of the profileable events. A second CPU is configured to analyze the generated profile data, while the execution and profile data generation continue on the first CPU, and to control the execution of the program on the first CPU based at least in part on the analysis of the collected profile data.

6789181, Sep 7, 2004

Nov 3, 1999

09/432753

John S. Yates - Needham MA
David L. Reese - Westborough MA
Korbin S. Van Dyke - Sunol CA
Paul H. Hohensee - Nashua NH

ATI International, SRL - Christ Church

G06F 944

712 4, 714 37

A method and computer for executing the method. A source program is translated into an object program, in a manner in which the translated object program has a different execution behavior than the source program. The translated object program is executed under a monitor capable of detecting any deviation from fully-correct interpretation before any side-effect of the different execution behavior is irreversibly committed. When the monitor detects the deviation, or when an interrupt occurs during execution of the object program, a state of the program is established corresponding to a state that would have occurred during an execution of the source program, and from which execution can continue. Execution of the source program continues primarily in a hardware emulator designed to execute instructions of an instruction set non-native to the computer.

6826748, Nov 30, 2004

Jun 24, 1999

09/339749

Paul H. Hohensee - Nashua NH
David L. Reese - Westborough MA
Korbin S. Van Dyke - Sunol CA
T. R. Ramesh - Newark CA
Shalesh Thusoo - Milpitas CA
Gurjeet Singh Saund - Mountain View CA
Niteen Aravind Patkar - Sunnyvale CA

ATI International SRL - Hastings

G06F 944

717130

A method and computer for performance of the method. While executing a program on a computer, the computer uses registers of a general register file for storage of instruction results. Profile information describing the profileable events is recorded into the general register file as the profileable events occur, without first capturing the information into a main memory of the computer.

6941545, Sep 6, 2005

May 28, 1999

09/322443

David L. Reese - Westborough MA, US
Paul H. Hohensee - Nashua NH, US
Korbin S. Van Dyke - Sunol CA, US
T. R. Ramesh - Newark CA, US
Shalesh Thusoo - Milpitas CA, US
Gurjeet Singh Saund - Mountain View CA, US
Niteen Aravind Patkar - Sunnyvale CA, US

ATI International SRL - Hastings

G06F009/44

717130, 717127, 717128, 717131, 717136, 717140, 712207, 712227, 711206, 711213

A computer. An instruction pipeline and memory access unit execute instructions in a logical address space of a memory of the computer. An address translation circuit translates address references generated by the program from the program's logical address space to the computer's physical address space. Profile circuitry is cooperatively interconnected with the instruction pipeline and configured to detect, without compiler assistance for execution profiling, occurrence of profilable events occurring in the instruction pipeline, and is cooperatively interconnected with the memory access unit to record profile information describing physical memory addresses referenced during an execution interval of the program.

6978462, Dec 20, 2005

Jun 11, 1999

09/332263

Michael C. Adler - Wayland MA, US
David L. Reese - Westborough MA, US
Paul H. Hohensee - Nashua NH, US
Stephen C. Purcell - Mountain View CA, US

ATI International SRL - Hastings

G06F003/00

719318

A computer having an instruction pipeline and profile circuitry. The profile circuitry detects and records, without compiler assistance for execution profiling, profile information describing a sequence of events occurring in the instruction pipeline. The sequence includes every event occurring during a profiled execution interval that matches time-independent selection criteria of events to be profiled. The recording continues until a predetermined stop condition is reached. The profile circuitry detects the occurrence of a predetermined condition, after a non-profiled interval of execution, and then commences the profiled execution interval.

7013456, Mar 14, 2006

Jun 16, 1999

09/334530

Korbin S. Van Dyke - Sunol CA, US
Paul H. Hohensee - Nashua NH, US
David L. Reese - Westborough MA, US
T. R. Ramesh - Newark CA, US
Shalesh Thusoo - Milpitas CA, US
Gurjeet Singh Saund - Mountain View CA, US
Stephen C. Purcell - Mountain View CA, US
Niteen Aravind Patkar - Sunnyvale CA, US

ATI International SRL - Christ Church

G06F 9/44

717130, 717131, 717217, 717128, 717129, 717154, 717158, 712208, 712215, 714 38, 714 39

A method and a computer for performance of the method. While executing a program on a computer, profileable events occurring in the instruction pipeline are detected. The instruction pipeline is directed to record profile information describing the profileable events essentially concurrently with the occurrence of the profileable events. The detecting and recording occur under control of hardware of the computer without software intervention.

7069421, Jun 27, 2006

Oct 28, 1999

09/429094

David L. Reese - Westborough MA, US
Paul H. Hohensee - Nashua NH, US
Korbin S. Van Dyke - Sunol CA, US
T. R. Ramesh - Newark CA, US

ATI Technologies, SRL - Christ Church

G06F 9/30

712209

A microprocessor chip, and methods for use in that microprocessor chip. The chip has instruction pipeline circuitry and address translation circuitry. Table lookup circuitry indexes into a table, the table having an entry associated with each corresponding address range translated by the address translation circuitry. Each entry of the table describes a likelihood of the existence of an alternate coding of instructions located in the respective corresponding address range. The table lookup circuitry retrieves a table entry corresponding to the address, and is operable as part of the basic instruction cycle of executing an instruction of a non-supervisor mode program executing on a computer. Interrupt circuitry is cooperatively designed with the instruction pipeline circuitry to trigger an interrupt on execution of an instruction of a process, synchronously based at least in part on a memory state of the computer and the address of the instruction, the architectural definition of the instruction not calling for an interrupt. A handler for the interrupt is responsive to the contents of the table to affect the instruction pipeline circuitry to effect control of an architecturally-visible data manipulation behavior or control transfer behavior of the instruction based on the contents of a table entry associated with the instruction.

7111290, Sep 19, 2006

Oct 22, 1999

09/425401

David L. Reese - Westborough MA, US
Paul H. Hohensee - Nashua NH, US

ATI International SRL - Hastings

G06F 9/45

717158

A method and a computer with circuitry configured for performance of the method are disclosed. During a profiled interval of an execution of a program on a computer, profile information is recorded describing the execution, without the program having been compiled for profiled execution. The program is coded in an instruction set in which an interpretation of an instruction depends on a processor mode not expressed in the binary representation of the instruction. The recorded profile information describes at least all events occurring during the profiled execution interval of the two classes: (1) a divergence of execution from sequential execution; and (2) a processor mode change that is not inferable from the opcode of the instruction that induces the processor mode change taken together with a processor mode before the mode change instruction. The profile information further identifies each distinct physical page of instruction text executed during the execution interval.