Paul A Laberge, 585986 Dellwood Ave, Saint Paul, MN 55126

6356953, Mar 12, 2002

Jun 6, 2000

09/588740

James W. Meyer - Shoreview MN
Paul A. Laberge - Coon Rapids MN

Micron Technology, Inc. - Boise ID

G06F 1300

709253, 710101, 710128, 370402

A system for communicating information between requester and target devices in a computer having a multiple bus architecture. The system supports deferred transactions of cache line read requests over a host bus, e. g. , the Pentium II or Pentium Pro (P ) bus. The system employs a host bridge to issue deferred transactions over the P bus without interrupting or involving the main processor. The system comprises a first device, electrically connected to the requester, which receives a request from the requester. The system further comprises a second device, electrically connected to the first device, which transmits the request with a defer enable signal over the P bus. The system further comprises a third device, electrically connected to the P bus, which communicates the request having a defer enable signal to the target.

6370644, Apr 9, 2002

Jul 18, 2000

09/618658

Paul A. LaBerge - Shoreview MN

Micron Technology, Inc. - Boise ID

G06F 15177

713 1, 713400, 710106, 710108

The present invention comprises a host bus clocked in a host clock domain, a secondary bus for receiving a reset command clocked in a secondary bus clock domain and a controller for dynamically delaying transactions on the host bus until the secondary bus is out of reset.

6425045, Jul 23, 2002

Jul 3, 2001

09/898277

Paul A. LaBerge - Shoreview MN

Micron Technology, Inc. - Boise ID

G06F 1200

711 5, 711105

A computer system includes a memory device including banks, and a memory interface coupled to the memory device. The memory interface is adapted to store requests that are associated with the banks. At least two of the requests are copending. The memory interface is adapted to determine whether the banks associated with the copending requests are idle and execute the requests based on the determination.

6467043, Oct 15, 2002

Jul 29, 1999

09/363790

Paul A. LaBerge - Shoreview MN

Micron Technology, Inc. - Boise ID

G06F 104

713401, 713400, 713500

A method for use with a computer system includes receiving a first data strobe signal from a bus and introducing a delay to the first data strobe signal to produce a second data strobe signal. The method includes determining whether the delay is within a predetermined range of delays, and if not, the method includes adjusting the delay to cause the delay to be within the predetermined range. The second data strobe signal is used to capture data from the bus.

6526497, Feb 25, 2003

Aug 20, 2001

09/933318

Paul A. LaBerge - Shoreview MN
Douglas A. Larson - Lakeville MN

Micron Technology, Inc. - Boise ID

G06F 1210

711207

A memory for storing address translation data includes one or more page table entry structures. Each page table entry structure includes a base address field to identify an allocated page of memory, a prior page field to identify zero or more allocated pages of memory that are sequential to and before that page of memory identified by the base address field, and a subsequent page field to identify zero or more allocated pages of memory that are sequential to and after that page identified by the base address field.

6601228, Jul 29, 2003

Sep 28, 2000

09/672649

Paul A. LaBerge - Shoreview MN

Micron Technology, Inc. - Boise ID

G06F 1750

716 16, 716 17, 716 2

An application specific integrated circuit has at least one standard cell, integrated circuit connection circuitry connected to the at least one standard cell and at least one programmable circuit that is connected or selectively connectable to the integrated circuit connection circuitry. The selected connection is made by metal mask changes if and when it is desirable to change the logic of the application specific circuit. The programmable circuit is a general-purpose logic block and may be reprogrammed to effect design changes.

6615345, Sep 2, 2003

Jul 29, 1999

09/363594

Paul A. LaBerge - Shoreview MN

Micron Technology, Inc. - Boise ID

G06F 104

713100, 713600, 714718, 365189, 365193, 365201, 365233, 711105, 711167

A computer system includes a memory bus, a memory device and a bridge. The memory device is adapted to furnish a data strobe signal to the memory bus and furnish other signals (to the memory bus) that are indicative of data. The bridge includes a first circuit that is adapted to use the other signals to capture the data in response to the data strobe signal. A second circuit of the bridge is coupled to the first circuit and is adapted to receive a data strobe signal from a memory bus. The data strobe signal is furnished by the memory device and includes a postamble. The second circuit is also adapted to monitor the data strobe signal to detect a signature of the data strobe signal that precedes the beginning of the postamble and prevent the first circuit from responding to the data strobe signal after detection of the signature.

6647541, Nov 11, 2003

Apr 9, 2001

09/832257

Paul A. LaBerge - Shoreview MN

Sun Microsystems, Inc. - Santa Clara CA

G06F 1750

716 18, 716 6, 716 3, 716 5

One embodiment of the present invention provides a system for synthesizing a circuit that allocates propagation delay between modules in the circuit based upon wireload information. The system receives a circuit divided into modules coupled together by a number of signal lines. The system defines a first set of timing constraints, and uses the first set of timing constraints to compile the circuit from a hardware description language specification into a first gate-level implementation. Next, the system performs a timing analysis on the first gate-level implementation to determine positive or negative slack values for the signal lines. These slack values specify amounts of extra propagation delay available on the signal lines. Next, the slack values are used to define a second set of timing constraints by allocating the slack values between the modules based upon wireload information. This wireload information may include such parameters as gate delays and drive strengths for gates coupled to the signal lines.