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Paul D Nuber, 663124 Majestic View Dr, Timnath, CO 80547

Known as:
Paul Douglas Nuber Paul K Nuber Paul D Huber
Related to:
Jessie E Evitt 33

Paul Nuber Phones & Addresses

3124 Majestic View Dr, Timnath, CO 80547    970-3778394   

1107 Twinberry Ct, Fort Collins, CO 80525    970-2299180   

1107 Twinberry Ct, Fort Collins, CO 80525    970-2317779   

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Paul D Nuber

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Work

Company: Broadcom Feb 2016 Position: Asic design engineer at avago technologies

Education

Degree: Master of Science, Masters School / High School: University of Wisconsin - Madison 1976 to 1985 Specialities: Computer Engineering

Skills

Asic • Vlsi • Static Timing Analysis • Ic • Semiconductors • Electrical Engineering • Physical Design • Eda • Timing Closure • Soc • Verilog • Cmos • Tcl • Mixed Signal • Circuit Design • Integrated Circuit Design • Semiconductor Industry • Low Power Design • Hardware Architecture • Drc • Application Specific Integrated Circuits • Rtl Design • Dft • Signal Integrity • Logic Design • Serdes • Primetime

Emails

p***[email protected]

Industries

Semiconductors
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Resumes

Paul Nuber Photo 21

Asic Design Engineer At Avago Technologies

Location:
Fort Collins, CO
Industry:
Semiconductors
Work:
Broadcom
Asic Design Engineer at Avago Technologies Avago Technologies 2005 - Jan 2016
Asic Design Engineer Agilent Technologies 1999 - 2005
Asic Design Engineer Hewlett-Packard 1985 - 1999
Asic Design Engineer
Education:
University of Wisconsin - Madison 1976 - 1985
Master of Science, Masters, Computer Engineering
Skills:
Asic, Vlsi, Static Timing Analysis, Ic, Semiconductors, Electrical Engineering, Physical Design, Eda, Timing Closure, Soc, Verilog, Cmos, Tcl, Mixed Signal, Circuit Design, Integrated Circuit Design, Semiconductor Industry, Low Power Design, Hardware Architecture, Drc, Application Specific Integrated Circuits, Rtl Design, Dft, Signal Integrity, Logic Design, Serdes, Primetime

Publications & IP owners

Us Patents

Method For Estimating And Displaying Wiring Congestion

US Patent:
6405358, Jun 11, 2002
Filed:
Oct 8, 1999
Appl. No.:
09/416015
Inventors:
Paul D Nuber - Ft Collins CO
Assignee:
Agilent Technologies, Inc. - Palo Alto CA
International Classification:
G06F 1750
US Classification:
716 12
Abstract:
Routing density estimates within a given integrated circuit are calculated from a proposed floor plan and block interconnect data. The chip is first divided into a number of grid areas, then the routing density is estimated for each grid area. This estimate is calculated by estimating grid areas that signals most likely will cross and summing probabilities. Both horizontal and vertical routing densities are estimated. The estimates for each grid area may then be saved in computer memory, printed, input to a spreadsheet, displayed on the screen, or returned in any other desired format.

System And Method For Dynamic Modification Of Integrated Circuit Functionality

US Patent:
6614260, Sep 2, 2003
Filed:
Jul 28, 2000
Appl. No.:
09/627696
Inventors:
M. Jason Welch - Ft. Collins CO
Paul D Nuber - Ft Collins CO
Assignee:
Agilent Technologies, Inc. - Palo Alto CA
International Classification:
H03K 19177
US Classification:
326 41, 326 10, 326 38
Abstract:
Programmable circuit blocks and programmable interconnection blocks are utilized to effectively modify the functionality of a section of the IC. The use of a fixed ion beam machine or similar device is unnecessary, allowing functional modifications of the IC by way of electrically programming the device. As a result, the IC designer is not limited in the number of ICs that may be modified, which facilitates faster testing of IC design changes. Also, an IC may be modified multiple times by simply reprogramming the device.

Bypass Capacitance Localization

US Patent:
6653858, Nov 25, 2003
Filed:
Dec 12, 2001
Appl. No.:
10/020366
Inventors:
Victoria Meier - Ft Collins CO
Paul D Nuber - Ft Collins CO
Assignee:
Agilent Technologies, Inc. - Palo Alto CA
International Classification:
H03K 19173
US Classification:
326 37, 326101, 326 27, 257532, 716 1
Abstract:
Localizing bypass capacitance for the purpose of reducing or eliminating noise in power supplies in an integrated circuit (IC). After a data path block of macro cells has been constructed by the IC designer, a determination is made as to which cells of the macro cells comprise functionality that will not be used by the IC when it is operating. At least a plurality of cells that are determined to be cells that comprise functionality that will not be used when the IC is operating are filled with bypass capacitors. Because there are typically a large number of cells that will not be used when the IC is operating, filling a plurality or all of these cells with bypass capacitors ensures that bypass capacitors will be located in close proximity to power supplies on the IC, which ensures that the bypass capacitors will be effective at reducing or eliminating noise in the power supplies.

Method Of Integrated Circuit Construction With Port Alignment And Timing Signal Buffering Within A Common Area

US Patent:
6734473, May 11, 2004
Filed:
Jan 27, 2000
Appl. No.:
09/491900
Inventors:
M. Jason Welch - Ft. Collins CO
Paul D Nuber - Ft Collins CO
Assignee:
Agilent Technologies, Inc. - Palo Alto CA
International Classification:
H01L 2710
US Classification:
257208, 257211, 257797, 257781, 257750
Abstract:
The present invention relates to a method of integrated circuit construction in which misaligned ports are linked via an alignment link made up of a wiring trace and signal buffer. The signal buffer and wiring trace are located within a common area of integrated circuit real estate.

Method And Apparatus For Preventing Buffers From Being Damaged By Electrical Charges Collected On Lines Connected To The Buffers

US Patent:
6775116, Aug 10, 2004
Filed:
Nov 1, 2001
Appl. No.:
10/046103
Inventors:
Paul D Nuber - Ft Collins CO
Gayvin E Stong - Fort Collins CO
Assignee:
Agilent Technologies, Inc. - Palo Alto CA
International Classification:
H02H 900
US Classification:
361 54, 361111, 361 915
Abstract:
An apparatus and method are provided for preventing buffers used to reduce delays on long lines of an IC from being damaged due to charge that collects on the buffers during manufacturing. In accordance with the present invention, a protection diode is included directly in at least each buffer that is used for this purpose, i. e. , for the purpose of preventing delays on long lines of the IC. By including a protection diode in at least each buffer that is used for this purpose, the present invention obviates the need for having to use tools during the IC design process to determine a suitable location for a protection diode.

Method And Apparatus For Ensuring Signal Integrity In A Latch Array

US Patent:
6894535, May 17, 2005
Filed:
Dec 18, 2001
Appl. No.:
10/025353
Inventors:
Jeffrey Thomas Robertson - Wellington CO, US
Victoria Meier - Ft Collins CO, US
Paul D Nuber - Ft Collins CO, US
Assignee:
Agilent Technologies, Inc. - Palo Alto CA
International Classification:
H03K019/173
US Classification:
326 46, 326 56
Abstract:
At least one column of a latch array includes a tri-state buffer in the upper portion of the column that receives the output of the uppermost group of latches of the column as its input, and which is enabled by a dump signal when a latch in the upper portion is addressed. When the dump signal that triggers the tri-state buffer is active, whatever is at the input of the tri-state buffer is driven by the buffer to the bottom of the latch array column, thereby providing the driven signal with sufficient strength to obviate transition timing and signal integrity problems. When the dump signal that triggers the tri-state buffer is not asserted, the tri-state buffer output exhibits high impedance, which isolates the lower portion of the latch array column from the upper portion of the latch array column, thereby preventing the capacitance associated with the line connecting the tri-state buffer to the output of the uppermost latch from affecting the driving ability of the latches in the lower portion of the column.

Possible Relatives

Dennis R Nuber  Edward A Nuber  Frank J Nuber  James R Nuber  Margaret E Nuber  Raymond P Nuber  Andrea L Nuber  Paul M Johnson  Paul Stamps  Paul B Stanaway 

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