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Peng Chaoju Peng, 5310120 Tularosa Pass, Austin, TX 78726

Peng Peng Phones & Addresses

10120 Tularosa Pass, Austin, TX 78726    512-7772760   

Leander, TX   

Cedar Park, TX   

Essex Junction, VT   

Blacksburg, VA   

Beacon, NY   

38 Thasha Ln APT G4, Essex Jct, VT 05452   

Work

Position: Sales Occupations

Education

Degree: Graduate or professional degree

Mentions for Peng Chaoju Peng

Peng Peng resumes & CV records

Resumes

Peng Peng Photo 43

Software Engineer At Ibm

Position:
Software Engineer at IBM
Location:
Austin, Texas Area
Industry:
Information Technology and Services
Work:
IBM
Software Engineer
Peng Peng Photo 44

Student At University Of San Diego

Location:
San Diego, California
Industry:
Education Management
Education:
University of San Diego 2009 - 2011
Peng Peng Photo 45

Peng Peng

Location:
United States
Peng Peng Photo 46

Peng Peng

Location:
United States
Peng Peng Photo 47

Peng Peng

Location:
United States

Publications & IP owners

Us Patents

System And Method For Estimating Leakage Current Of An Electronic Circuit

US Patent:
8239794, Aug 7, 2012
Filed:
Sep 29, 2009
Appl. No.:
12/568985
Inventors:
Bhavna Agrawal - Milton NY, US
David J. Hathaway - Underhill VT, US
Pravin P. Kamdar - Leander TX, US
Peng Peng - Essex Junction VT, US
David W. Winston - Asheville NC, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
G06F 17/10
US Classification:
716106, 716104, 716105, 716108, 716111, 716115, 716120, 716136, 703 2, 703 13, 703 14
Abstract:
Disclosed are embodiments of a system and of an associated method for estimating the leakage current of an electronic circuit. The embodiments analyze a layout of an electronic circuit in order to identify all driven and non-driven nets within the electronic circuit, to identify all of the driven net-bounded partitions within the electronic circuit (based on the driven and non-driven nets), and to identify, for each driven net-bounded partition, all possible states of the electronic circuit that can leak. Then, using this information, the embodiments estimate the leakage current of the electronic circuit. This is accomplished by first determining, for each state of each driven net-bounded partition, a leakage current of the driven net-bounded partition and a probability that the state will occur in the driven net-bounded partition during operation of the electronic circuit. Then, for each state of each driven net-bounded partition, the leakage current of the driven net-bounded partition and the state probability are multiplied together. The results are then aggregated.

Method For Estimating Aggregate Leakage Of Transistors

US Patent:
7487480, Feb 3, 2009
Filed:
May 12, 2008
Appl. No.:
12/118857
Inventors:
Bhavna Agrawal - Milton NY, US
David J. Hathaway - Underhill VT, US
Peng Peng - Essex Junction VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
G06F 17/17
G06F 17/11
US Classification:
716 5, 703 2, 703 16
Abstract:
A method of estimating a leakage for a plurality of transistors in an integrated circuit that accounts for narrow channel effects includes determining an expected total leaking transistor width for the collection; determining an expected total number of leaking transistors for the collection; determining an average width of a leaking transistor from the expected total leaking transistor width and expected total number of leaking transistors; estimating a leakage for a transistor of the average width; and determining the estimated leakage for the collection of transistors by multiplying the leakage for a transistor of the average width by the expected total number of leaking transistors for the collection.

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