Peter Breger resumes & CV records
Resumes
Peter Breger
Location:
San Francisco Bay Area
Industry:
Electrical/Electronic Manufacturing
Peter N Breger1130 Royal Ln, San Carlos, CA 94070
Peter Breger Phones & Addresses
1130 Royal Ln, San Carlos, CA 94070
Winnetka, CA
22212 Belleau Ct, Calabasas, CA 91302
Social networks
Peter N Breger
Linkedin
Industries
Electrical/Electronic Manufacturing
Mentions for Peter N Breger
Publications & IP owners
Us Patents
Driver With Transmission Path Loss Compensation
US Patent:
6360180, Mar 19, 2002
Filed:
May 10, 1999
Appl. No.:
09/309134
Inventors:
Peter Breger - Calabasas CA
Assignee:
Teradyne, Inc. - Boston MA
International Classification:
G01D 300
US Classification:
702108, 327317
Abstract:
A driver for applying a deterministic waveform along a lossy transmission path to a device-under-test is disclosed. The driver includes a signal generator for producing a substantially square-wave signal at an output node and an injector coupled to the output node for modifying the square-wave signal to pre-compensate for expected losses along the lossy path.
Hybrid Tester Architecture
US Patent:
6885961, Apr 26, 2005
Filed:
Feb 28, 2002
Appl. No.:
10/090585
Inventors:
Peter Breger - Calabasas CA, US
Grady Borders - West Hills CA, US
Grady Borders - West Hills CA, US
Assignee:
Teradyne, Inc. - Boston MA
International Classification:
G06F011/26
US Classification:
702117, 702118, 702125, 714724
Abstract:
A hybrid tester architecture for testing a plurality of semiconductor devices in parallel is disclosed. The hybrid tester architecture includes per-pin formatting circuitry having data input circuitry and clock input circuitry and shared timing circuitry coupled to the clock input circuitry. The shared timing circuitry generates programmed timing signals. Per-pin data circuitry couples to the data input circuitry and generates drive data and expected data values associated with each individual device pin. The per-pin formatting circuitry responds to the programmed timing signals to produce tester waveforms in accordance with the per-pin data.
Serial Switch Driver Architecture For Automatic Test Equipment
US Patent:
6137310, Oct 24, 2000
Filed:
Feb 19, 1999
Appl. No.:
9/253175
Inventors:
Peter Breger - Calabasas CA
Assignee:
Teradyne, Inc. - Boston MA
International Classification:
H03K 1900
US Classification:
326 56
Abstract:
A tristate circuit for driving three signal levels to a pin of a device-under-test is disclosed. The tristate circuit includes a driver having an output at a first signal level and adapted for coupling to the pin. A first switching unit couples to the output and responds to a programmed signal. The first switching unit operates to selectively alter the first signal level to a second signal level. A second switching unit connects serially to the first switch. The second switching unit responds to a second programmed signal and operates to cooperate with the first switch to alter the second signal level to a third signal level.
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