Peter James Sallaway, 5011279 Senda Luna Llena, San Diego, CA 92130

6975674, Dec 13, 2005

May 12, 2000

09/570331

Abhijit M. Phanse - Santa Clara CA, US
Peter J. Sallaway - San Diego CA, US
Thulasinath G. Manickam - San Diego CA, US

National Semiconductor Corporation - Santa Clara CA

H04L005/16

375219, 375232, 375345, 375350, 455136, 455138, 4552321

There is disclosed a mixed mode equalization system for use in a transceiver capable of operating in a high frequency Ethernet local area network (LAN). The mixed mode equalization system comprises: 1) an adaptive analog equalization filter for amplifying a first high frequency component of an incoming analog signal by a first adjustable gain factor to produce an analog filtered incoming signal; 2) an analog-to-digital converter (ADC) for converting the analog filter incoming signal to a first incoming digital signal; 3) a digital finite impulse response (FIR) filter for amplifying a second high frequency component of the first incoming digital signal factor to produce a digital filtered incoming signal; 4) a digital FIR controller for modifying at least one digital filter coefficient of the digital FIR filter according to a signal error associated with a digital output of the digital FIR filter; and 5) an analog equalization controller for modifying the first adjustable gain factor associated with the adaptive analog equalization filter according to a value of the at least one digital filter coefficient.

6980644, Dec 27, 2005

May 12, 2000

09/570078

Peter J. Sallaway - San Diego CA, US
Thulasinath G. Manickam - San Diego CA, US
Sreen Raghavan - La Jolla CA, US

National Semiconductor Corporation - Santa Clara CA

H04M001/00
H04M009/00
H04M009/08

379391, 379392, 37940601

There is disclosed an echo canceller circuit for use in a full duplex transceiver of the type comprising a line driver capable of sending analog transmit signals through a cable and comprising a line receiver capable of receiving analog receive signals from the cable. An echo canceller impedance model circuit is coupled to an output of the line driver and is coupled to an input of the line receiver. The echo canceller impedance model circuit generates an echo canceller current that is equal in magnitude and opposite in phase to a current that represents signal echoes that are present in the analog receive signals. The echo canceller impedance model circuit has a variable impedance for generating the echo canceller current. The variable impedance has at least one variable resistor and at least one variable capacitor. The values of resistance and capacitance in the echo canceller impedance model circuit are varied in response to control signals from a echo canceller control circuit to compensate for and cancel signal echoes.

7050517, May 23, 2006

Apr 28, 2000

09/560109

Peter J. Sallaway - San Diego CA, US
Sreen Raghavan - La Jolla CA, US

National Semiconductor Corporation - Santa Clara CA

H04B 1/10

375350

A detector system for high-speed Ethernet LAN is described. One embodiment includes a detector system having N one dimensional sequence detector equalizers in combination with an N-dimensional traceback decoder. The detector system detects N-dimensional symbols transmitted over N separate transport channels to N one-dimensional receivers. In one embodiment, Gigabit Ethernet receiver includes a four-wire transport to four 1D receivers and a 4D detector. The 4D detector in one embodiment is a parity code detector. In another embodiment, the 4D detector is a 4D trellis code detector.

7065133, Jun 20, 2006

Jun 28, 2004

10/878966

Abhijit M. Phanse - Santa Clara CA, US
Peter J. Sallaway - San Diego CA, US
James B. Wieser - Pleasanton CA, US

National Semiconductor Corporation - Santa Clara CA

H04B 1/38
H03H 7/30

375219, 375232

There is disclosed a transceiver for use in a high speed Ethernet local area network (LAN). The transceiver comprises: 1) front-end analog signal processing circuitry comprising: a) a line driver for transmitting an outgoing analog signal to an external cable; b) a DC offset correction circuit for reducing a DC component in an incoming analog signal; c) an echo canceller; d) an automatic gain control (AGC) circuit; and e) an adaptive analog equalization filter. The transceiver also comprises: 2) an analog-to-digital converter (ADC) for converting the analog filter incoming signal to a first incoming digital signal; and 3) digital signal processing circuitry comprising: a) a digital finite impulse response (FIR) filter; b) a digital echo cancellation circuit to produce a reduced-echo incoming digital signal; c) a digital automatic gain control (AGC) circuit; and d) a digital base line wander circuit.

7236757, Jun 26, 2007

Feb 6, 2002

10/071771

Sreen A. Raghavan - La Jolla CA, US
Thulasinath G. Manickam - San Diego CA, US
Peter J. Sallaway - San Diego CA, US
Gerard E. Taylor - Laguna Nigel CA, US

Vativ Technologies, Inc. - San Diego CA

H04B 1/04
H04L 27/36
H04K 1/10

455203, 455 91, 4551142, 4551151, 455132, 375219, 375260, 375298

A communication system is disclosed that allows high data-rate transmission of data between components. N-bit parallel data is transmitted in K-frequency separated channels on the transmission medium so as to fully take advantage of the overall bandwidth of the transmission medium. Additionally, a cross-channel interference filter in a receiver section corrects for cross-channel interference in the communication system. As a result, a very high data-rate transmission can be accomplished with low data-bit transmission on individual channels. A transmitter system and a receiver system are described for the communication system.

7248890, Jul 24, 2007

Feb 6, 2004

10/773750

Sreen A. Raghavan - La Jolla CA, US
Thulasinath G. Manickam - San Diego CA, US
Peter J. Sallaway - San Diego CA, US
Gerard E. Taylor - Laguna Nigel CA, US

Vativ Technologies, Inc. - San Diego CA

H04B 7/00
H04Q 7/20

455522, 455 68, 455 69, 455 6711, 455 6713, 4551271, 4551272, 4551273, 4552261, 4552451, 4552452, 4552321, 4552342, 4552351, 379318, 379252, 398137

A transceiver according to some embodiments of the present invention receives data from a plurality of frequency separated transmission channels from a complementary transmitter of another transceiver and adjusts the power output of certain channels in a transmitter of the receiver. Upon start-up, the power output levels of signals in individual channels in the transmitter can be preset. A power balance can determine new power output levels of the transmitter from parameters in the receiver while receiving data transmitted by a similarly situated complementary transmitter in a second transceiver coupled to the transceiver. In some embodiments, a complementary receiver of the other transceiver determines the power outputs of the transmitter and the power levels are transmitted to the transmitter by the other transceiver.

7254198, Aug 7, 2007

Apr 28, 2000

09/561086

Tulsi Manickam - Rancho Pensaquitos CA, US
Peter J. Sallaway - San Diego CA, US
Sreen A. Raghavan - La Jolla CA, US
Abhijit M. Phanse - Cupertino CA, US
James B. Wieser - Pleasanton CA, US

National Semiconductor Corporation - Santa Clara CA

H04B 1/10

375348, 375233, 375350

A receiver system suitable for a local area network contains an analog pre-filter ( or ), an analog-to-digital converter (), a digital equalizer (), and a decoder (). A symbol-information-carrying input analog signal (y), or a first intermediate analog signal generated from the input analog signal, is filtered by filtering circuitry in the pre-filter to produce a filtered analog signal (Z) with reduced intersymbol interference. The filtering circuitry operates according to a transfer function such as (bs+1)/(as+as+1) or (1−V)+VPF(s) where Vis adaptively varied. The analog-to-digital converter provides analog-to-digital signal conversion. The equalizer provides digital signal equalization to produce an equalized digital signal (a′) as a stream of equalized digital values. The decoder converts the equalized digital values, or intermediate digital values generated from the equalized digital values, into a stream of symbols.

7333603, Feb 19, 2008

Dec 27, 2005

11/320520

Peter J. Sallaway - San Diego CA, US
Thulasinath G. Manickam - San Diego CA, US
Sreen Raghavan - La Jolla CA, US

National Semiconductor Corporation - Santa Clara CA

H04M 1/00
H04M 9/00

379391

There is disclosed an echo canceller circuit for use in a full duplex transceiver of the type comprising a line driver capable of sending analog transmit signals through a cable and comprising a line receiver capable of receiving analog receive signals from the cable. An echo canceller impedance model circuit is coupled to an output of the line driver and is coupled to an input of the line receiver. The echo canceller impedance model circuit generates an echo canceller current that is equal in magnitude and opposite in phase to a current that represents signal echoes that are present in the analog receive signals. The echo canceller impedance model circuit has a variable impedance for generating the echo canceller current. The variable impedance has at least one variable resistor and at least one variable capacitor. The values of resistance and capacitance in the echo canceller impedance model circuit are varied in response to control signals from a echo canceller control circuit to compensate for and cancel signal echoes.