Peter E Weiler, 8875-5919 Alii Dr APT CC4, Kailua Kona, HI 96740

5814847, Sep 29, 1998

Feb 2, 1996

8/595684

Elias E. Shihadeh - Nazareth, IL
Peter M. Weiler - Palo Alto CA

National Semiconductor Corp. - Santa Clara CA

H05K 102
H01L 2702

257209

A multi-chip module interconnection substrate includes at least two layers of conductive traces separated by an intervening layer of insulating material. The conductive traces include straight segments and diagonal segments. A plurality of conductive vias, each including conductive via wing extensions, allow one to make electrical connections between the various conductive trace layers. The conductive vias are formed such that a narrow, non-conductive, gap exists between the via wing extensions and the conductive traces. The multi-chip module interconnection substrate is then programmed, e. g. in the field, by making electrical connections between the via wing extensions and the conductive traces using e. g. wire bonds or ball bonds formed by conventional wire bonding equipment.

5559056, Sep 24, 1996

Jan 13, 1995

8/372386

Peter M. Weiler - Palo Alto CA

National Semiconductor Corporation - Santa Clara CA

H01L 2144

437195

A method for fabricating bond pads on a semiconductor device that reduces intermetallic growth between a metallization layer and a bonding layer is discussed. Initially a metallization layer is deposited over a substrate. Following steps include depositing a barrier layer over the metallization layer, masking a portion of the barrier layer, and etching the barrier layer and the metallization layer. Etching of the barrier and masking layers is performed utilizing the barrier layer mask as a mask for both the barrier layer and the metallization layer. Further steps include depositing a non-conductive layer conformally overlying the barrier layer, masking a portion of the non-conductive layer, and etching the non-conductive layer. Etching the non-conductive layer forms an exposed region of the barrier layer. A later step of this method includes forming a bond layer over the exposed region of the barrier layer, with one possible formation method utilizing an electrolysis process.

5455745, Oct 3, 1995

Jul 26, 1993

8/083142

Peter M. Weiler - Palo Alto CA
Thomas S. Burke - San Francisco CA

National Semiconductor Corporation - Santa Clara CA

H05K 502

361813

A transfer molded high lead count plastic semiconductor package is described. The packaged IC chip is mounted upon a suitable leadframe and the bonding pads wire bonded to the leadframe fingers. To avoid wire shorting, due to wire sweep during transfer molding, the wires are first coated with an insulative material.

5527742, Jun 18, 1996

Jun 28, 1995

8/495388

Peter M. Weiler - Palo Alto CA
Thomas S. Burke - San Francisco CA

National Semiconductor Corporation - Santa Clara CA

H01L 2160

437211

A transfer molded high lead count plastic semiconductor package is described. The packaged IC chip is mounted upon a suitable leadframe and the bonding pads wire bonded to the leadframe fingers. To avoid wire shorting, due to wire sweep during transfer molding, the wires are first coated with an insulative material.