BackgroundCheck.run
Search For

Min Sik Woo, 495142 Shady Ave, San Jose, CA 95129

Known as:
Min S Woo Min C Woo Min M Woo Sik Woo
Related to:
Kyu Young Sung 61

Min Woo Phones & Addresses

5142 Shady Ave, San Jose, CA 95129    408-3400831   

3558 Jasmine Crk, San Jose, CA 95135    408-2388079   

Milton, VT   

Burlington, VT   

West Chester, PA   

Downingtown, PA   

University Park, PA   

Get Report
Control this profile

Mentions for Min Sik Woo

Min Woo resumes & CV records

Resumes

Min Woo Photo 33

Quality And Reliability Lead

Location:
5142 Shady Ave, San Jose, CA 95129
Industry:
Computer Hardware
Work:
Esperanto Technologies, Inc
Quality and Reliability Lead Barefoot Networks
Senior Quality and Reliability Manager Apple May 1, 2014 - Sep 2017
Q and R Engineer Nvidia Oct 2010 - May 2014
Reliability Engineering Manager Nvidia May 2005 - Sep 2010
Senior Reliability Engineer Ibm Feb 2001 - Apr 2005
Esd and Latch-Up Engineer
Education:
Penn State University 1995 - 2000
Bachelors, Bachelor of Science, Electrical Engineering Coatesville Area High School
Pennsylvania State University
Skills:
Reliability, Reliability Engineering, Esd, Esd Control, Failure Analysis, Circuit Design, Ic, Semiconductor Industry, Silicon, Cmos, Product Engineering, Semiconductors, Mixed Signal, Soc, Analog, Asic, Electronics, Debugging, Integrated Circuits, Application Specific Integrated Circuits
Languages:
English
Min Woo Photo 34

Min Woo

Min Woo Photo 35

Min Woo

Min Woo Photo 36

Min Woo

Min Woo Photo 37

Owner

Work:
Vnv
Owner
Min Woo Photo 38

Min Woo

Location:
United States

Publications & IP owners

Us Patents

Vertical Silicon Controlled Rectifier Electro-Static Discharge Protection Device In Bi-Cmos Technology

US Patent:
2007002, Feb 1, 2007
Filed:
Jul 27, 2005
Appl. No.:
11/161230
Inventors:
Kiran Chatty - Williston VT, US
Robert Gauthier - Hinesburg VT, US
Andreas Stricker - Essex Junction VT, US
Min Woo - Milton VT, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
H01L 27/082
US Classification:
257575000
Abstract:
A vertical silicon controlled rectifier (SCR) that directs an electro-static discharge (ESD) current directly to ground from the input/output pad. The vertical SCR is includes a vertical NPN and a vertical PNP that creates a very good SCR exhibiting very low ohmic on-resistance. The vertical SCR provides a low on-resistance and fast turn on, and can be adjusted to alter the trigger voltage value, holding voltage and how it is triggered. It can be optimized to trigger under ESD events and discharge the ESD current effectively to ground.

Mixed Voltage Tolerant Electrostatic Discharge Protection Silicon Controlled Rectifier With Enhanced Turn-On Time

US Patent:
7005686, Feb 28, 2006
Filed:
Jul 26, 2005
Appl. No.:
11/161184
Inventors:
Kiran V. Chatty - Williston VT, US
Mujahid Muhammad - Essex Junction VT, US
Andreas D. Stricker - Essex Junction VT, US
Min Woo - Milton VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 29/66
H01L 21/33
US Classification:
257154, 257155, 438133
Abstract:
Disclosed is a method for increasing substrate resistance in a silicon controlled rectifier in order to decrease turn on time so that the silicon controlled rectifier may be used as an effective electrostatic discharge protection device to protect against HBM, MM and CDM discharge events. Additionally, disclosed is an improved SCR structure that is adapted for use as an electrostatic discharge device to protect against human body model events by delivering an electrostatic discharge current directly to a ground rail. The improved SCR structure incorporates various features for increasing substrate resistance and, thereby, for decreasing turn on time. These features include a second n-well that functions as an obstacle to current flow, a narrow current flow channel between co-planar buried n-bands connected to a lower portion of the second n-well, a zero threshold voltage area, and an external resistor electrically connected between the SCR and the ground rail.

Method And Apparatus For Testing Interconnection Reliability Of A Ball Grid Array On A Testing Printed Circuit Board

US Patent:
2014011, Apr 24, 2014
Filed:
Oct 24, 2012
Appl. No.:
13/659425
Inventors:
- Santa Clara CA, US
Min Woo - Santa Clara CA, US
Assignee:
NVIDIA CORPORATION - Santa Clara CA
International Classification:
G01R 31/26
US Classification:
32476202
Abstract:
An apparatus for determining an electrical reliability of a ball grid array (BGA) assembly of an integrated circuit is presented. The assembly comprises a testing printed circuit board (PCB) having an integrated circuit (IC) test region located thereon. Vias extend through the testing PCB from a surface to an underside thereof within the IC test region. Each via has an IO pad or ground pad electrically connectable thereto. An IC package having an IC die connected thereto by solder bumps is connected to the IC test region by solder balls, such that each of the IO pads is electrically connectable to a respective pair of the solder balls and solder bumps by the vias. A method of testing interconnection reliability of the BGA using the apparatus is also presented.

Possible Relatives

Cynthia R Woo  Deana K Woo  Dae S Woo  Deanna T Woo  Daisy Woo  Deborah L Woo  Daniel N Woo  Min J Jun  Min J Jung  Min Y Kang 

NOTICE: You may not use BackgroundCheck or the information it provides to make decisions about employment, credit, housing or any other purpose that would require Fair Credit Reporting Act (FCRA) compliance. BackgroundCheck is not a Consumer Reporting Agency (CRA) as defined by the FCRA and does not provide consumer reports.