Philip R Trask Deceased2201 El Grande St, Hemet, CA 92545

5034091, Jul 23, 1991

Apr 27, 1990

7/515813

Philip A. Trask - Laguna Hills CA
Gabriel G. Bakhit - Huntington Beach CA
Vincent A. Pillai - Irvine CA
Kirk R. Osborne - Los Angeles CA
Kathryn J. Berg - Long Beach CA
Gary B. Warren - Huntington Beach CA

Hughes Aircraft Company - Los Angeles CA

B44C 122
B29C 3700
C23F 102
C03C 1500

156643

A via (26) is formed through a dielectric layer (8) separating two conductive layers (16,28) by establishing a laterally erodible mask (18) over the dielectric (8), with a window (24) over the desired via location. The mask (18) and exposed dielectric material (8) are eroded simultaneously, preferably by reactive ion etching, producing a via (26) through the dielectric (8) which expands laterally as vertical erosion proceeds. The erosion conditions, the materials for the mask (18) and dielectric (8), and the initial window (24) taper are selected so that the final via (26) is tapered at an angle of less than about 45. degree. to the lower metal layer (6), and preferably about 30. degree. -45. degree. , to enable a generally uniform width for the upper metallization (28) in the via (26). A non-erodible mask (10) is established over the dielectric layer (8) lateral to the via (26) during fabrication to prevent the propagation of pinhole defects from the erodible mask (18) into the dielectric (8), and is normally removed prior to completing the structure.

5827775, Oct 27, 1998

Nov 12, 1997

8/968378

Robert S. Miles - Monrovia CA
Philip A. Trask - Laguna Hills CA
Vincent A. Pillai - Irvine CA

Raytheon Comapny - Lexington MA

H01L 2128

438622

Phase mask laser machining procedures for fabricating high density fine pattern feature electrical interconnection structures. Conductor patterns are fabricated using a phase mask laser patterned dielectric layer as a conductor wet etch masking layer, or by subtractively removing metal using holographic phase mask laser micromachining. In accordance with the present invention, a substrate is provided, a first layer of dielectric material is formed on the substrate, a metal layer is formed on the first layer of dielectric material, and a second layer of dielectric material is then formed on the metal layer. A phase mask is disposed above the second layer of dielectric material that has a predefined phase pattern therein defining a metal conductor pattern that corresponds to an interconnect structure. The second layer of dielectric material is then processed using the phase mask to form the interconnect structure. In a first procedure, the second layer of dielectric material is irradiated through the phase mask using laser energy to remove portions of the second layer of dielectric material and expose the metal layer to define the metal conductor pattern and to provide a dielectric etch mask.

5691245, Nov 25, 1997

Oct 28, 1996

8/738558

Gabriel G. Bakhit - Huntington Beach CA
Vincent A. Pillai - Irvine CA
George Averkiou - Upland CA
Philip A. Trask - Laguna Hills CA

HE Holdings, Inc. - Los Angeles CA

H01L 2160

437209

Methods of forming two-sided high density multilayer interconnect (HDMI) structures on a relatively large carrier and subsequently releasing and removing one or more structures to provide useable flexible interconnects or decals. In general, a carrier is provided and a release layer is formed on the carrier. Flexible high density multilayer interconnect structures are fabricated on the release layer. The release layer is processed to release and remove one or more flexible HDMI structures from the carrier. The carrier may be an ultraviolet transparent substrate, such as quartz, for example, and the release layer may be a polyimide layer. The HDMI structures are released by irradiating the release layer through the transparent carrier using ultraviolet radiation from an ultraviolet radiation source. Alternatively, a silicon carrier may be used that has a metal or silicon dioxide release layer formed thereon. The HDMI structures are released from the metal or silicon dioxide release layer by using wet etching procedures.

5474956, Dec 12, 1995

Mar 14, 1995

8/403610

Philip A. Trask - Laguna Hills CA
Vincent A. Pillai - Irvine CA

Hughes Aircraft Company - Los Angeles CA

H01L 21268
H01L 21312

437173

A method of patterning a metallized substrate using a thin partially cured etch block layer. In accordance with the method, a substrate is provided and a layer of metal, such as aluminum, is deposited on the substrate. A thin layer of organic dielectric material, such as polyimide, is deposited over the layer of metal. The thin layer of organic dielectric material is deposited to a thickness on the order one micron, for example, which is thin enough to have etch resistance when acting as an etch block layer for subsequent wet etch patterning of the layer of metal, and thick enough to have no pinhole defects. The deposited thin organic dielectric layer is then partially cured. The underlying layer of metal is then patterned and wet etched using the partially cured thin organic dielectric material as the blocking layer. An additional thick layer of organic dielectric material is then deposited or coated over the patterned layer of metal and partially cured organic dielectric layer. The partially cured organic dielectric layer and the additional thick organic dielectric material are then simultaneously full cured.

5817541, Oct 6, 1998

Mar 20, 1997

8/822092

George Averkiou - Upland CA
Philip A. Trask - Laguna Hills CA

Raytheon Company - Lexington MA

H01L 2144

438107

Methods of producing a chip scale package that enables any chip with peripheral bond pads to be converted to an area array chip scale package suitable for chip on board assembly. The present invention produces the equivalent of a flip chip die when a chip supplier does not provide one. Processing is performed that provides thin film metal interconnections between the chip bond pads and area array bond pads on the bottom of the package. High reliability thin film metal interconnections are thus provided that connect the bond pads of the chip to the area array bond pads to permit external connection to the chip.

5311404, May 10, 1994

Jun 30, 1992

7/906637

Philip A. Trask - Laguna Hills CA
Vincent A. Pillai - Irvine CA
Thomas J. Gierhart - Fountain Valley CA

Hughes Aircraft Company - Los Angeles CA

H05K 118

361762

An electrical interconnection substrate (20) is prepared to receive both wire bonded and soldered connections (60,64,66) by forming a dielectric solder mask (30) over the substrate (20), with openings (36) in the mask (30) to expose the contact pads (22) for which soldered connections are desired. The substrate (20) is exposed to a molten solder alloy (44) in a wave soldering process that dissolves the wire bonding material (28) (preferably gold) from the exposed pads (22) and deposits solder bonding pads (52) in its place. Excess solder is then removed from the substrate, and openings (54) are formed through the solder mask (30) to expose the wire bond contact pads (22'). The selective dissolving of gold bonding layers (28) and their replacement by solder pads (52) prevents the establishment of brittle gold-solder intermetallics, and the deposited solder (52) requires no further heat treatment for correct alloy formation.

5840622, Nov 24, 1998

Aug 27, 1996

8/703854

Robert S. Miles - Monrovia CA
Philip A. Trask - Laguna Hills CA
Vincent A. Pillai - Irvine CA

Raytheon Company - Lexington MA

H01L 2128

438622

Phase mask laser machining procedures for fabricating high density fine pattern feature electrical interconnection structures. Conductor patterns are fabricated using a phase mask laser patterned dielectric layer as a conductor wet etch masking layer, or by subtractively removing metal using holographic phase mask laser micromachining. In accordance with the present invention, a substrate is provided, a first layer of dielectric material is formed on the substrate, a metal layer is formed on the first layer of dielectric material, and a second layer of dielectric material is then formed on the metal layer. A phase mask is disposed above the second layer of dielectric material that has a predefined phase pattern therein defining a metal conductor pattern that corresponds to an interconnect structure. The second layer of dielectric material is then processed using the phase mask to form the interconnect structure. In a first procedure, the second layer of dielectric material is irradiated through the phase mask using laser energy to remove portions of the second layer of dielectric material and expose the metal layer to define the metal conductor pattern and to provide a dielectric etch mask.

5445311, Aug 29, 1995

Oct 13, 1994

8/324271

Philip A. Trask - Laguna Hills CA
Vincent A. Pillai - Irvine CA
Thomas J. Gierhart - Fountain Valley CA

Hughes Aircraft Company - Los Angeles CA

B23K 3100
H01L 2102

228175

An electrical interconnection substrate (20) is prepared to receive both wire bonded and soldered connections (60,64,66) by forming a dielectric solder mask (30) over the substrate (20), with openings (36) in the mask (30) to expose the contact pads (22) for which soldered connections are desired. The substrate (20) is exposed to a molten solder alloy (44) in a wave soldering process that dissolves the wire bonding material (28) (preferably gold) from the exposed pads (22) and deposits solder bonding pads (52) in its place. Excess solder is then removed from the substrate, and openings (54) are formed through the solder mask (30) to expose the wire bond contact pads (22'). The selective dissolving of gold bonding layers (28) and their replacement by solder pads (52) prevents the establishment of brittle gold-solder intermetallics, and the deposited solder (52) requires no further heat treatment for correct alloy formation.