Phillip Rasmussen resumes & CV records
Resumes
Phillip Rasmussen
Phillip Rasmussen
Phillip A Rasmussen, 53Boise, ID
Phillip Rasmussen Phones & Addresses
Boise, ID
Twin Falls, ID
San Luis Obispo, CA
Goleta, CA
Mentions for Phillip A Rasmussen
Publications & IP owners
Us Patents
Method And Apparatus For Properly Disabling High Current Parts In A Parallel Test Environment
US Patent:
6522161, Feb 18, 2003
Filed:
Jul 5, 2001
Appl. No.:
09/898047
Inventors:
Aron T. Lunde - Boise ID
Phillip A. Rasmussen - Boise ID
Phillip A. Rasmussen - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G01R 3126
US Classification:
324765, 3241581
Abstract:
A parallel test system and method for testing integrated circuit devices which can reliably prevent devices that should not be active due to a blown fuse from generating random data signals which can adversely impact the test results of other chips being tested are disclosed. The state of each fuse that protects a respective socket on a test board is determined by a controller, such as an Application Specific Integrated Circuit (ASIC), built onto the test board. When it is determined that a specific fuse is open, i. e. , the fuse has blown due to a high current condition, the device inserted into the socket protected by the fuse will have its I/O lines disabled by the controller, thereby effectively shutting off the device completely and preventing it from generating and transmitting random data to the test device.
Sub-Instruction Repeats For Algorithmic Pattern Generators
US Patent:
8607111, Dec 10, 2013
Filed:
Aug 30, 2006
Appl. No.:
11/513087
Inventors:
Phillip Rasmussen - Boise ID, US
Charles Snodgrass - Boise ID, US
Charles Snodgrass - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G01R 31/28
G06F 11/00
G06F 11/00
US Classification:
714738, 714744
Abstract:
An integrated circuit tester is described that utilizes methods of programming parallel coupled Algorithmic Pattern Generators (APGs) to generate test vector sequences and part commands with sub-instruction repeats. This enables simpler test programming and ease of test conversion to new part speed grades, steppings, or part designs. In one embodiment, a sub-instruction repeat is utilized to enable adjustment of the timing of test vector sequences and part commands sent to an integrated circuit device under test (DUT) so that the test can be adjusted for new part speed grades and/or steppings. In another embodiment, a sub-instruction repeats are utilized to enable adjustment of the timing of a memory device inputs, memory commands and test vector sequences so that the test can be adjusted for new memory device speed grades.
Method And Apparatus For Properly Disabling High Current Parts In A Parallel Test Environment
US Patent:
6275058, Aug 14, 2001
Filed:
Jan 26, 1999
Appl. No.:
9/236649
Inventors:
Aron T. Lunde - Boise ID
Phillip A. Rasmussen - Boise ID
Phillip A. Rasmussen - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G01R 3126
US Classification:
324765
Abstract:
A parallel test system and method for testing integrated circuit devices which can reliably prevent devices that should not be active due to a blown fuse from generating random data signals which can adversely impact the test results of other chips being tested are disclosed. The state of each fuse that protects a respective socket on a test board is determined by a controller, such as an Application Specific Integrated Circuit (ASIC), built onto the test board. When it is determined that a specific fuse is open, i. e. , the fuse has blown due to a high current condition, the device inserted into the socket protected by the fuse will have its I/O lines disabled by the controller, thereby effectively shutting off the device completely and preventing it from generating and transmitting random data to the test device.
Masked Training And Analysis With A Memory Array
US Patent:
2022035, Nov 3, 2022
Filed:
May 3, 2021
Appl. No.:
17/306559
Inventors:
- Boise ID, US
Phillip A. Rasmussen - Boise ID, US
Thomas Hein - Munich, DE
Phillip A. Rasmussen - Boise ID, US
Thomas Hein - Munich, DE
International Classification:
G06F 3/06
Abstract:
Methods, systems, and devices for masked training and analysis with a memory array are described. A memory device may operate in a first mode in which a maximum transition avoidance (MTA) decoder for a memory array of the memory device is disabled. During the first mode, the memory device may couple an input node of the MTA decoder with a first output node of a first decoder, such as a first pulse amplitude modulation (PAM) decoder. The memory device may operate in a second mode in which the MTA decoder for the memory array is enabled. During the second mode, the memory device may couple the input node of the MTA decoder with a second output node of a second decoder, such as a second PAM decoder.
Fail Compare Procedure
US Patent:
2022022, Jul 21, 2022
Filed:
Jan 19, 2021
Appl. No.:
17/152039
Inventors:
- Boise ID, US
Phillip A. Rasmussen - Boise ID, US
Phillip A. Rasmussen - Boise ID, US
International Classification:
G06F 11/263
G06F 16/23
G06F 16/23
Abstract:
Methods, systems, and devices for a fail compare procedure are described. An apparatus may include a host device coupled with a memory device. An application specific integrated circuit (ASIC) associated with the host device (e.g., included in, coupled with) may include a set of comparators that output first bit information that includes respective states of at least two bits of data read from the memory device. The host device may compare (e.g., at the ASIC) the first bit information to second bit information that includes respective expected states of the at least two bits. Based on the comparison, the host device may determine whether a state of at least one bit of the first bit information is different than a state of a corresponding bit of the second bit information, and may output one or more signals including indications of a fail to a counter of the ASIC.
Masked Training And Analysis With A Memory Array
US Patent:
2023005, Feb 23, 2023
Filed:
Oct 19, 2022
Appl. No.:
18/047893
Inventors:
- Boise ID, US
Phillip A. Rasmussen - Boise ID, US
Thomas Hein - Munich, DE
Phillip A. Rasmussen - Boise ID, US
Thomas Hein - Munich, DE
International Classification:
G06F 3/06
Abstract:
Methods, systems, and devices for masked training and analysis with a memory array are described. A memory device may operate in a first mode in which a maximum transition avoidance (MTA) decoder for a memory array of the memory device is disabled. During the first mode, the memory device may couple an input node of the MTA decoder with a first output node of a first decoder, such as a first pulse amplitude modulation (PAM) decoder. The memory device may operate in a second mode in which the MTA decoder for the memory array is enabled. During the second mode, the memory device may couple the input node of the MTA decoder with a second output node of a second decoder, such as a second PAM decoder.
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