Prakash Chauhan, 5416812 Potter Ct, Los Gatos, CA 95032

6578099, Jun 10, 2003

Jan 4, 2000

09/477756

Robert G. Bassman - Austin TX
Tuyet-Huong T. Nguyen - Austin TX
Wai-Ming R. Chan - Austin TX
Prakash Chauhan - Austin TX

Dell USA, L.P. - Round Rock TX

G06F 1300

710301, 710303

A computer system and a method for allocating power to hot-plugged adapter cards placed in a card slot so as to delay, the power allocation until a user is clear of the adapter card. The computer system conventionally includes a processor, a card slot in data communication with the processor, a memory in data communication with the processor, and a power supply in electrical communication with the processor. The memory stores computer-readable data that includes code to be operated on by the processor to allocate power to the card slot upon both a detection of a change of state of the card slot and the occurrence of a predefined system event. The predefined system event is typically a system interrupt that is generated in response to an activation of a switch in electrical communication with the processor.

2023005, Feb 16, 2023

Jul 28, 2022

17/876110

- Mountain View CA, US
Prakash Chauhan - Los Gatos CA, US

G06F 3/06

Aspects of the disclosure are directed to hardware interconnects and corresponding devices and systems for non-coherently accessing data in shared memory devices. Data produced and consumed by devices implementing the hardware interconnect can read and write directly to a memory device shared by multiple devices, and limit coherent memory transactions to relatively smaller flags and descriptors used to facilitate data transmission as described herein. Devices can communicate less data on input/output channels, and more data on memory and cache channels that are more efficient for data transmission. Aspects of the disclosure are directed to devices configured to process data that is read from the shared memory device. Devices, such as hardware accelerators, can receive data indicating addresses for different data buffers with data for processing, and non-coherently read or write the contents of the data buffers on a memory device shared between the accelerators and a host device.