Praveen S Mosalikanti, 487903 NW 169Th Ave, Portland, OR 97229

8031017, Oct 4, 2011

Jun 26, 2009

12/492940

Praveen Mosalikanti - Portland OR, US
Nasser A. Kurd - Portland OR, US
Timothy M. Wilson - Aloha OR, US

Intel Corporation - Santa Clara CA

H03K 3/03
G01R 23/02

331108D, 331 57, 331185, 702 65, 702 71, 702 75, 702 79, 702118, 702179

Described herein is the method and apparatus for determining frequency of an oscillator coupled with one or more analog devices, and for determining within-die or across-die variations in an analog property associated with the one or more analog devices, the determining based on the oscillator frequency. The analog property includes output signal swing, bandwidth, offset, gain, and delay line linearity and range. The one or more analog devices include input-output (I/O) buffer, analog amplifier, and delay line. The method further comprises updating a simulation model file based on the determining of the within-die and/or across-die variations of the analog property.

8248124, Aug 21, 2012

Jun 3, 2010

12/793533

Praveen Mosalikanti - Portland OR, US
Nasser A. Kurd - Portland OR, US
Christopher P. Mozak - Beaverton OR, US

Intel Corporation - Santa Clara CA

H03L 7/06

327158, 327149

A low power delay-locked loop (DLL) is presented. In one embodiment, the DLL includes a phase detector which includes a reference input and a feedback input to determine a phase difference. The DLL also includes a controller to determine whether to provide a signal to both the reference input and the feedback input such that the reference input and the feedback input receive an identical input, for example, during low power operation.

8258837, Sep 4, 2012

Dec 17, 2009

12/640842

Praveen Mosalikanti - Portland OR, US
Nasser Kurd - Portland OR, US

Intel Corporation - Santa Clara CA

H03L 7/06

327158, 327149

Methods and systems to generate multiple phases of a clock may include a delay locked loop (DLL) to generate a bias signal to control a delay time through DLL delay elements in response to a first clock, and a plurality of a quadrature slave delay lines (SDLs), each to generate a plurality of successively phase shifted clocks over a quadrant of a corresponding selected phase of a second clock. The SDLs may be biased with the DLL bias signal to control phase differences between the generated clocks. One or more phase interpolators, such as contention based phase interpolators, may be coupled to outputs of each SDL. A frequency of the second clock may be equal to or greater than a frequency of the first clock. The SDLs may be implemented with fewer delay elements than the DLL.

8350610, Jan 8, 2013

Jul 21, 2010

12/840691

Praveen Mosalikanti - Portland OR, US
Harishankar Sridharan - Folsom CA, US
Jacob Schneider - Austin TX, US
Pushkar Gorur - Bangalore, IN
Nasser A. Kurd - Portland OR, US

Intel Corporation - Santa Clara CA

H03K 3/02

327198, 327143, 327535, 327 73

Described herein is a method and apparatus to wake-up analog bias signals with minimum delay. The apparatus comprises a first logic unit operable to adjust a signal level of a gated bias signal via a first predetermined signal in response to a power-down event; a comparator operable to compare the gated bias signal with an un-gated bias signal, and operable to generate an output signal indicating the comparison result; and a self-timed logic unit coupled to the comparator and operable to generate a wake-up signal in response to an end of the power-down event and the output signal.

8502612, Aug 6, 2013

Aug 3, 2011

13/197525

Praveen Mosalikanti - Portland OR, US
Nasser A. Kurd - Portland OR, US
Timothy M. Wilson - Aloha OR, US

Intel Corporation - Santa Clara CA

G01R 23/02
G01R 27/00
H03K 3/03

331108D, 331 44, 331 57, 331185, 702 65, 702 71, 702 75, 702 79, 702118, 702179

Described herein is the method and apparatus for determining frequency of an oscillator coupled with one or more analog devices, and for determining within-die or across-die variations in an analog property associated with the one or more analog devices, the determining based on the oscillator frequency. The analog property includes output signal swing, bandwidth, offset, gain, and delay line linearity and range. The one or more analog devices include input-output (I/O) buffer, analog amplifier, and delay line. The method further comprises updating a simulation model file based on the determining of the within-die and/or across-die variations of the analog property.

8552781, Oct 8, 2013

Dec 17, 2009

12/640763

Praveen Mosalikanti - Portland OR, US
Nasser Kurd - Portland OR, US

Intel Corporation - Santa Clara CA

H03K 3/00
H03K 5/13
H03H 11/16

327243, 327231

Methods and systems to adjust a phase difference between signals, such as to perform quadrature phase correction. First and second signals are digitally compared, such as with exclusive OR circuitry, to provide a comparison signal having a duty cycle representative of a phase difference between the signals. A phase delay of one or both of the first and second signals is adjusted until the duty cycle of the comparison signal corresponds to a desired phase difference. In a clock and data recovery system, the signals may correspond to a zero degree phase of a first phase interpolator and a ninety degree phase of a second phase interpolator, and digital codes to the first and second phase interpolators may be adjusted to provide a fifty percent duty cycle in the comparison signal.

2007021, Sep 20, 2007

Mar 15, 2006

11/377140

Zhanping Chen - Portland OR, US
Kevin Zhang - Portland OR, US
Jonathan Douglas - Portland OR, US
Praveen Mosalikanti - Hillsboro OR, US
Gregory Taylor - Portland OR, US

G11C 17/00
G11C 7/02

365096000, 365208000

An apparatus, a method, and a system for a fuse array are disclosed herein. In some embodiments, fuse array may comprise a plurality of fuse cells and a single sense amplifier coupled to plurality of fuse cells to asynchronously sense one or more voltages output by the plurality of fuse cells, one fuse cell at a time.

2008015, Jun 26, 2008

Dec 22, 2006

11/644381

Zhanping Chen - Portland OR, US
Jonathan P. Douglas - Portland OR, US
Praveen Mosalikanti - Portland OR, US
Kevin Zhang - Portland OR, US
Gregory F. Taylor - Portland OR, US

G11C 17/16

365 96

An apparatus, a method, and a system for a fuse cell array are disclosed herein. A plurality of fuse cells are arranged in an array. One or more fuse cells include a pair of fuse devices to output a pair of voltages, respectively, wherein the pair of fuse devices are redundantly programmed. A sense amplifier is coupled to the plurality of fuse cells to read the pair of voltage outputs from each of the plurality of fuse cells, respectively. A comparator circuit is coupled to the sense amplifier to compare the pair of voltage outputs for each of the plurality of fuse cells and to output the compared result.