Qi F Zhang, 371837 NE 175Th St, Seattle, WA 98155

7091890, Aug 15, 2006

Aug 17, 2004

10/919901

Paul T. Sasaki - Sunnyvale CA, US
Jason R. Bergendahl - Sunnyvale CA, US
Atul Ghia - San Jose CA, US
Hassan Bazargan - San Jose CA, US
Ketan Sodha - Fremont CA, US
Jian Tan - Fremont CA, US
Qi Zhang - Milpitas CA, US
Suresh Menon - Sunnyvale CA, US

Xilinx, Inc. - San Jose CA

H03M 9/00

341100, 341 59

A serializer-deserializer instantiated in configurable logic of an integrated circuit is described. The serializer-deserializer includes an input deserializer and an output serializer, which may be commonly coupled via an input/output pad. Each of the serializer and deserializer may be configured for an operating mode selected from a Single Data Rate mode and a Double Data Rate mode. The serializer-deserializer may be used as part of a synchronous interface.

7302099, Nov 27, 2007

Nov 10, 2003

10/704785

Qi Zhang - Redmond WA, US
Henry A. Rowley - New Castle WA, US
Ahmad A. Abdulkader - Sammamish WA, US
Angshuman Guha - Woodinville WA, US

Microsoft Corporation - Redmond WA

G06K 9/18
G06K 9/00

382186, 382185, 382187

Ink strokes of cursive writing are segmented to make the cursive writing more like print writing, particularly with respect to the number of strokes of a character. A stroke-segmentation module first finds the local extrema points on a stroke of input ink. Then the local extrema points are stepped through, two (or three) at a time. The stroke-segmentation module may compare the three (or four) ink segments that are adjacent to the two (or three) local extrema points to a set of predefined stroke-segmentation patterns to find a closest matching pattern. Strokes are then segmented based on a stroke-segmentation rule that corresponds to the closest matching pattern. Additional stroke segmentation may be performed based on the change of curvature of the segmented ink strokes. Then, a character-recognition module performs character recognition processing by comparing the segmented ink strokes to prototype samples at least some of which have been similarly segmented.

7369702, May 6, 2008

Nov 7, 2003

10/702663

Ahmad A. Abdulkader - Sammamish WA, US
Brian Leung - Cambridge MA, US
Henry Allan Rowley - New Castle WA, US
Qi Zhang - Redmond WA, US

Microsoft Corporation - Redmond WA

G06K 9/00
G06K 9/62

382187, 382161, 382224

Input handwritten characters are classified as print or cursive based upon numerical feature values calculated from the shape of an input character. The feature values are applied to inputs of an artificial neural network which outputs a probability of the input character being print or cursive. If a character is classified as print, it is analyzed by a print character recognizer. If a character is classified as cursive, it is analyzed using a cursive character recognizer. The cursive character recognizer compares the input character to multiple prototype characters using a Dynamic Time Warping (DTW) algorithm.

7468615, Dec 23, 2008

Mar 28, 2007

11/729201

Jian Tan - Fremont CA, US
Qi Zhang - Milpitas CA, US

Xilinx, Inc. - San Jose CA

H03K 19/094
H03K 19/0175
H03L 5/00

326 68, 327333

A high-speed, area-efficient level shifter includes transistors having a variety of oxide thicknesses. The level shifter has a protection circuit stage, and a current mirror stage that allows the level shifter to perform over a wide voltage range at a high frequency. The level shifter maintains rise time, fall time, and duty cycle over a wide range of input and output voltage levels.

7480361, Jan 20, 2009

Jul 12, 2004

10/889553

Qi Zhang - Milpitas CA, US
Atul Ghia - San Jose CA, US

Xilinx, Inc. - San Jose CA

H03D 3/24

375376

Method and apparatus for phase lock detection is described. More particularly, a phase lock detection circuit () includes a synchronization circuit () coupled to receive a reference signal () and configured to provide a derivative signal (). A phase lock detector () is coupled to receive the reference signal () and the derivative signal () and is configured to provide a cycle lock signal () indicating whether a phase lock exists within a lock window () for a clock cycle.

7496547, Feb 24, 2009

Jun 10, 2005

11/150852

Ahmad A. Abdulkader - Redmond WA, US
Ioannis A. Drakopoulos - Redmond WA, US
Qi Zhang - Redmond WA, US

Microsoft Corporation - Redmond WA

G06F 15/18

706 20, 706 15, 706 48, 382159

Handwriting recognition techniques employing a personalized handwriting recognition engine. The recognition techniques use examples of an individual's previous writing style to help recognize new pen input from that individual. The techniques also employ a shape trainer to select samples of an individual's handwriting that accurately represent the individual's writing style, for use as prototypes to recognize subsequent handwriting from the individual. The techniques also alternately or additionally employ an intelligent combiner to combine the recognition results from the personalized recognition engine and the conventional recognition engine (or engines). The combiner may use a comparative neural network to combine the recognition results from multiple recognition engines. The combiner alternately may use a rule-based system based on prior knowledge of different recognition engines.

7551646, Jun 23, 2009

Sep 10, 2004

10/938151

Qi Zhang - Milpitas CA, US
Jason R. Bergendahl - Sunnyvale CA, US
Atul V. Ghia - San Jose CA, US
Suresh M. Menon - Sunnyvale CA, US

XILINX, Inc. - San Jose CA

H04J 3/06

370503, 370516, 375376

A data alignment and deskewing module includes a delay calibration unit, a data alignment and deskew unit, and a delay unit. The delay calibration unit is operably coupled to generate a reference signal based on a reference clock and a mirrored delay line output signal. The data alignment and deskew unit is operably coupled to determine a delay selection signal based on a delayed and deskewed representation of an input data stream and propagation delay of a line on which the input data stream is received. The delay unit is operably coupled to produce the delayed and deskewed representation of the input data stream based on the reference signal and the delay selection signal.

7589557, Sep 15, 2009

Apr 18, 2006

11/405901

Jason R. Bergendahl - Sunnyvale CA, US
Qi Zhang - Milpitas CA, US
Jian Tan - Fremont CA, US
Matthew H. Klein - Redwood City CA, US

Xilinx, Inc. - San Jose CA

H03K 19/173

326 41, 326 37

An input/output (I/O) structure includes a delay element usable for the input path, the output path, or both input and output paths in a user design. In a first mode, the delay element is included in the input path. In a second mode, the delay element is included in the output path. In a third mode, the I/O structure includes the delay in both outgoing signal paths and incoming signal paths, e. g. , by utilizing an output tristate signal to control the direction of the delay line. When the output buffer is driving, the delay is inserted in the output path. When the output buffer is tristated, the delay is inserted in the input path. Thus, a single delay element is dynamically shared by both input and output signals that use the same I/O pad. In an optional fourth mode, the delay element is bypassed by both input and output signals.