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Qiaolin L Zhang, 47829 Blair Ave, Sunnyvale, CA 94087

Qiaolin Zhang Phones & Addresses

829 Blair Ave, Sunnyvale, CA 94087    408-7490976   

100 Whisman Rd, Mountain View, CA 94043    650-6250699   

1070 Jackson St, Albany, CA 94706    510-5261529   

Berkeley, CA   

33300 Mission Blvd, Union City, CA 94587    510-6759763   

Santa Clara, CA   

100 N Whisman Rd APT 3614, Mountain View, CA 94043   

Social networks

Qiaolin L Zhang

Linkedin

Work

Company: Google Jan 2016 Position: Senior software engineer

Education

Degree: Master of Science, Doctorates, Masters, Doctor of Philosophy School / High School: University of California, Berkeley 2001 to 2006 Specialities: Electrical Engineering, Computer Science, Engineering, Design

Skills

Algorithms • Software Development • C++ • C • Java • Objective C • Php • Sql • Cloud Computing • Ios Development • Android Sdk • Python • Perl • Tcl • Android • Matlab • Eda • Lithography • Programming

Languages

English • Mandarin

Industries

Computer Software

Mentions for Qiaolin L Zhang

Qiaolin Zhang resumes & CV records

Resumes

Qiaolin Zhang Photo 12

Senior Software Engineer

Location:
San Francisco, CA
Industry:
Computer Software
Work:
Google
Senior Software Engineer
Vmware Nov 2011 - Apr 2013
Senior Member of Technical Staff
Storm8/Teamlava Mar 2011 - Oct 2011
Software Engineer
Synopsys May 2006 - Feb 2011
Staff Engineer
Amd May 2004 - Apr 2006
Intern Researcher
Education:
University of California, Berkeley 2001 - 2006
Master of Science, Doctorates, Masters, Doctor of Philosophy, Electrical Engineering, Computer Science, Engineering, Design
University of Science and Technology of China 1996 - 2001
Bachelors, Bachelor of Science, Electrical Engineering
Skills:
Algorithms, Software Development, C++, C, Java, Objective C, Php, Sql, Cloud Computing, Ios Development, Android Sdk, Python, Perl, Tcl, Android, Matlab, Eda, Lithography, Programming
Languages:
English
Mandarin

Publications & IP owners

Us Patents

Method And Apparatus For Modeling An Apodization Effect In An Optical Lithography System

US Patent:
7681172, Mar 16, 2010
Filed:
Jan 29, 2007
Appl. No.:
11/699805
Inventors:
Qiaolin Zhang - Union City CA, US
Paul VanAdrichem - Cupertino CA, US
Laurent Depre - Revel, FR
Qiliang Yan - Portland OR, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06F 17/50
G03F 1/00
G03C 5/00
US Classification:
716 19, 716 4, 716 21, 430 5, 430 30
Abstract:
One embodiment of the present invention provides a system that accurately predicts an apodization effect in an optical lithography system for manufacturing an integrated circuit. During operation, the system starts by collecting an apodization-effect-induced spatial transmission profile from the optical lithography system. The system then constructs an apodization model based on the spatial transmission profile. Next, the system enhances a lithography model for the optical lithography system by incorporating the apodization model into the lithography model, wherein the enhanced lithography model accurately predicts the effects of apodization on the optical lithography system.

Bulk Image Modeling For Optical Proximity Correction

US Patent:
8006203, Aug 23, 2011
Filed:
Aug 28, 2008
Appl. No.:
12/200523
Inventors:
Yongfa Fan - San Jose CA, US
Qiaolin Zhang - Mountain View CA, US
Bradley J. Falch - Round Rock TX, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06F 17/50
G06F 19/00
G03F 1/00
G21K 5/00
G06K 9/00
US Classification:
716 54, 716 55, 716 51, 716111, 716136, 700 98, 700121, 700120, 430 5, 378 35, 382144, 382145, 382154
Abstract:
A method is described herein for predicting lateral position information about a feature represented in an integrated circuit layout for use with an integrated circuit fabrication process, where the process projects an image onto a resist. The method includes providing a lateral distribution of intensity values of the image at different depths with the resist. Next, the lateral position of an edge point of the feature is predicted in dependence upon a particular resist development time, and further in dependence upon the image intensity values at more than one depth within the resist.

Modeling Critical-Dimension (Cd) Scanning-Electron-Microscopy (Cd-Sem) Cd Extraction

US Patent:
8196068, Jun 5, 2012
Filed:
Apr 30, 2009
Appl. No.:
12/387383
Inventors:
Qiaolin Zhang - Mountain View CA, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06F 17/50
G06F 19/00
G03F 1/00
G21K 5/00
G06K 9/00
US Classification:
716 53, 716 52, 716 54, 716111, 430 5, 378 35, 382144, 382145, 700 98, 700121
Abstract:
One embodiment of the present invention relates to a process that models critical-dimension (CD) scanning-electron-microscopy (CD-SEM) extraction during photolithography process model calibration. During operation, the process receives measured CD values which were obtained using a CD-SEM extraction process, wherein the CD-SEM extraction process determines a measured CD value for a feature by measuring multiple CD values of the feature along multiple electron beam scans. The process then determines simulated CD values, wherein a simulated CD value is determined based at least on a set of CD extraction cut-lines evenly placed around the target feature. During subsequent photolithography process model calibration, the process fits a parameter that models an aspect of the photolithography process based at least on both the measured CD values and the simulated CD values.

Modeling Thin-Film Stack Topography Effect On A Photolithography Process

US Patent:
8423917, Apr 16, 2013
Filed:
Jul 30, 2009
Appl. No.:
12/512677
Inventors:
Hua Song - San Jose CA, US
James P. Shiely - Aloha OR, US
Qiaolin Zhang - Mountain View CA, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06F 17/50
US Classification:
716 50, 716 51
Abstract:
One embodiment of the present invention provides a system that determines image intensity at a location in a photoresist (PR) layer on a wafer. During operation, the system receives a set of masks which were used to generate one or more patterned layers of a multilayer structure on the wafer, wherein a patterned layer includes a set of reflectors on a top surface of the patterned layer, which correspond to patterns in a patterned-layer mask in the set of masks, wherein a reflector reflects light from a light source during a photolithography process. The system then generates a first virtual mask based on the first mask and the patterned-layer mask, wherein the first virtual mask uses a clear area to model a reflector in the set of reflectors. Next, the system determines the image intensity value at the location on the PR layer based at least on the first mask and the first virtual mask.

Modeling An Arbitrarily Polarized Illumination Source In An Optical Lithography System

US Patent:
8527253, Sep 3, 2013
Filed:
Sep 6, 2007
Appl. No.:
11/851021
Inventors:
Qiaolin Zhang - Sunnyvale CA, US
Hua Song - San Jose CA, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06F 17/50
US Classification:
703 13
Abstract:
One embodiment of the present invention provides a system that accurately models polarization states of an illumination source in an optical lithography system for manufacturing integrated circuits. During operation, the system starts by receiving a two-dimensional (2D) grid map for an illumination source pupil in the optical lithography system. The system then constructs a source-polarization model for the illumination source by defining a polarization state at each grid point in the grid map. Next, the system enhances a lithography model for the optical lithography system by incorporating the source-polarization model into the lithography/OPC model.

Method And Apparatus For Modeling A Vectorial Polarization Effect In An Optical Lithography System

US Patent:
2009007, Mar 12, 2009
Filed:
Sep 6, 2007
Appl. No.:
11/851011
Inventors:
Qiaolin Zhang - Sunnyvale CA, US
Hua Song - San Jose CA, US
Kevin D. Lucas - Austin TX, US
Assignee:
SYNOPSYS, INC. - Mountain View CA
International Classification:
G06F 17/50
US Classification:
716 19
Abstract:
One embodiment of the present invention provides a system that accurately models polarization effects in an optical lithography system for manufacturing integrated circuits. During operation, the system starts by receiving a polarization-description grid map for a lens pupil in the optical lithography system. The system then constructs a pupil-polarization model by defining a vectorial matrix at each grid point in the grid map, wherein the vectorial matrix specifies a pupil-induced polarization effect on an incoming optical field at the grid point. Next, the system enhances a lithography model for the optical lithography system by incorporating the pupil-polarization model into the lithography/OPC model. The system then uses the enhanced lithography model to perform convolutions with circuit patterns on a mask in order to simulate optical lithography pattern printing.

Modeling A Sector-Polarized-Illumination Source In An Optical Lithography System

US Patent:
2009026, Oct 22, 2009
Filed:
Apr 16, 2008
Appl. No.:
12/104122
Inventors:
Qiaolin Zhang - Mountain View CA, US
Hua Song - San Jose CA, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06G 7/62
G06F 17/10
US Classification:
703 2
Abstract:
One embodiment of the present invention provides a system that constructs a source polarization model to simulate a piecewise-constant-linear polarization-configuration of an illumination source in an optical lithography system. During operation, the system starts by partitioning an illumination pupil plane of the illumination source into a set of sectors to match a physical implementation of the illumination source. Next, the system constructs the source polarization model for the illumination source by individually specifying a constant-linear polarization-state within each sector to match the polarization-configuration of the illumination source.

Optimizing Critical Dimension Uniformity Utilizing A Resist Bake Plate Simulator

US Patent:
7334202, Feb 19, 2008
Filed:
Jun 3, 2005
Appl. No.:
11/145327
Inventors:
Bhanwar Singh - Morgan Hill CA, US
Qiaolin Zhang - Albany CA, US
Iraj Emami - Austin TX, US
Joyce S. Oey Hewett - Austin TX, US
Luigi Capodiece - Santa Cruz CA, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 17/50
US Classification:
716 4
Abstract:
A system for optimizing critical dimension uniformity in semiconductor manufacturing processes is provided. The system comprises a bake plate simulator to model a physical bake plate. A finite element analysis engine uses information from the bake plate simulator to calculate missing information. A lithography simulator predicts outcomes of a lithography process using information from the bake plate simulator and the finite element analysis engine. The system can be used in a predictive capacity or as part of a process control system.

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