Raphael B Weiss, 66109 Cedar Dr W, Hicksville, NY 11803

7631176, Dec 8, 2009

Jul 24, 2006

11/459413

Raphael Weiss - Plainview NY, US
Richard E. Wahler - St. James NY, US
John D. Virzi - Bayside NY, US
Randy B. Goldberg - Massapequa NY, US

Standard Microsystems Corporation - Hauppauge NY

G06F 9/00
H03L 7/00

713 1, 713100, 327143, 327151

A resistor/capacitor identification detection (RCID) circuit may provide system level identification of hardware (e. g. circuit board ID) through a single pin interface, by identifying up to a specified number of more than two quantized RC time constant states by measuring the discharge and charge times of an external RC circuit coupled to the single pin. The RCID circuit may initiate the discharge followed by a charging of the external RC circuit. The signal developed at the signal pin may be provided to the input of a threshold detector, with the threshold set at a specified percentage of a supply voltage used for operating the RCID circuit. The digitized output of the threshold detector may be used to gate a counter, after having been filtered through an input glitch rejection filter. A resolution of the counter may be determined by a high frequency clock used for clocking the counter. The numeric values of the charge and discharge times may be stored in data registers comprised in the RCID circuit.

7707437, Apr 27, 2010

May 3, 2006

11/417855

Alan D. Berenbaum - New York NY, US
Raphael Weiss - Plainview NY, US

Standard Microsystems Corporation - Hauppauge NY

G06F 1/00

713300, 713320, 713323, 709208, 709253

A power state broadcast mechanism. A master device may broadcast a message through the use of a protocol to each of one or more slave devices to inform the slave devices of the power state of a computer system. The broadcast message may include a protocol header indicating the start of the broadcast transaction, a function type parameter indicating the type of broadcast transaction, and power state data indicating the power state of the computer system. Each of the slave devices may read the protocol header to detect the start of a broadcast transaction, and the function type parameter to determine the type of broadcast transaction. If the function type parameter indicates a power state broadcast transaction, each of the slave devices may read the power state data included in the broadcast message and determine whether to adjust the current power state of the slave device.

7917716, Mar 29, 2011

Aug 31, 2007

11/848808

Alan D. Berenbaum - New York NY, US
Raphael Weiss - Plainview NY, US

Standard Microsystems Corporation - Hauppauge NY

G06F 12/14
G06F 9/24

711163, 711E12091, 713 2, 713193

System and method for protecting data in a system including a main processor, an embedded controller, and a memory. In response to a power-on-reset (POR), access to the memory is enabled, e. g. , access by the embedded controller. First data is read from the memory (e. g. , by the embedded controller) in response to the enabling, where the first data are usable to perform security operations for the system prior to boot-up of the main processor. The first data are used, e. g. , by the embedded controller, to perform one or more security operations for the system, then access to the memory, e. g. , by the embedded controller, is disabled, where after the disabling the memory is not accessible, e. g. , until the next POR initiates enablement.

7917741, Mar 29, 2011

Apr 10, 2007

11/733599

Drew J. Dutton - Austin TX, US
Alan D. Berenbaum - New York NY, US
Richard E. Wahler - St. James NY, US
Raphael Weiss - Plainview NY, US

Standard Microsystems Corporation - Hauppauge NY

G06F 9/00
G06F 15/177
G06F 1/24
G06F 21/00
G06F 12/14
G06F 7/04
G06F 17/30
G08B 29/00

713 1, 713 2, 713100, 713186, 713194, 726 2, 726 28, 726 34

System and method for performing pre-boot security verification in a system that includes a host processor and memory, an embedded microcontroller with an auxiliary memory, e. g. , an on-chip ROM, or memory controlled to prohibit user-tampering with the contents of the memory, and one or more pre-boot security components coupled to the embedded microcontroller. Upon power-up, but before host processor boot-up, the embedded microcontroller accesses the auxiliary memory and executes the program instructions to verify system security using the one or more pre-boot security components. The one or more pre-boot security components includes at least one identity verification component, e. g. , a smart card, or a biometric sensor, e. g. , a fingerprint sensor, a retinal scanner, and/or a voiceprint sensor, etc. , and/or at least one system verification component, e. g.

7966379, Jun 21, 2011

Aug 31, 2006

11/469267

Alan D. Berenbaum - New York NY, US
Raphael Weiss - Plainview NY, US

Standard Microsystems Corporation - Hauppauge NY

G06F 15/16

709208, 709217, 709248, 709213, 710 15, 710105, 719318, 719321, 714E11023, 714 48

In-band event polling mechanism. A master device may initiate a polling transaction to poll at least a subset of a plurality of slave devices for event information. In response to the polling transaction, at least one of the subset of slave devices may transmit event information to the master device. The event information may correspond to at least one of a plurality of asynchronous event types. If the event type associated with the received event information is an event notification for an embedded processor of the master device, the master device may forward the event information to the embedded processor. Otherwise, if the event type associated with the received event information is an event notification for a device external to the master device (e. g. , a host processor), the master device may translate the event information to a protocol associated with the event type and forward the event information to the external device.

7991943, Aug 2, 2011

Oct 26, 2007

11/924826

Alan D. Berenbaum - New York NY, US
Richard E. Wahler - St. James NY, US
Raphael Weiss - Plainview NY, US

Standard Microsystems Corporation - Hauppauge NY

G06F 12/02

711103, 711163, 711E12008

System and method for implementing one time programmable (OTP) memory using embedded flash memory. A system-on-chip (SoC) includes a cleared flash memory array that includes an OTP block, including an OTP write inhibit field that is initially deasserted, a flash memory controller, and a controller. Data are written to the OTP block, including setting the OTP write inhibit field to signify prohibition of subsequent writes to the OTP block. The SoC is power cycled, and, in response, at least a portion of the OTP block is latched in a volatile memory, including asserting an OTP write inhibit bit based on the OTP write inhibit field, after which the OTP block is not writeable. In response to each subsequent power cycling, the controller is held in reset, the latching is performed, the controller is released from reset, and the flash array, now write protected, is configured to be controlled by the controller.

8006095, Aug 23, 2011

Aug 31, 2007

11/848854

Alan D. Berenbaum - New York NY, US
Raphael Weiss - Plainview NY, US

Standard Microsystems Corporation - Hauppauge NY

H04L 9/32

713180, 713 2, 713168, 713169, 713193, 711152, 711163

System and method for authenticating data or program code via a configurable signature. Configuration information is retrieved from a protected first memory, e. g. , an on-chip register, where the configuration information specifies a plurality of non-contiguous memory locations that store the signature, e. g. , in an on-chip memory trailer. The signature is retrieved from the plurality of non-contiguous memory locations based on the configuration information, where the signature is useable to verify security for a system. The signature corresponds to specified data and/or program code stored in a second memory, e. g. , in off-chip ROM. The specified data and/or program code may be copied from the second memory to a third memory, and a signature for the specified data and/or program code calculated based on the configuration information. The calculated signature may be compared with the retrieved signature to verify the specified data and/or program code.

8239603, Aug 7, 2012

May 3, 2006

11/417391

Drew J. Dutton - Austin TX, US
Alan D. Berenbaum - New York NY, US
Raphael Weiss - Plainview NY, US

Standard Microsystems Corporation - Hauppauge NY

G06F 13/40

710307, 710 66, 710315

A system including a serialized secondary bus architecture. The system may include an LPC bus, an I/O controller, a serialized secondary bus, and at least one slave device. The LPC bus may be connected to the I/O controller, and the at least one slave device may be connected to the I/O controller via the serialized secondary bus. The serialized secondary bus has a reduced pin count relative to the LPC bus. The I/O controller may receive bus transactions from the LPC bus. The I/O controller may translate and forward LPC bus transactions to the at least one device over the secondary bus. The I/O controller may include a processing unit. The processing unit may initiate bus transactions intended for the at least one slave device. The I/O controller may also include a bus arbitration unit. The bus arbitration unit may arbitrate ownership of the secondary bus between the processing unit and the LPC bus.