Rajesh R Gupta, 47Folsom, CA

6594808, Jul 15, 2003

Nov 5, 1999

09/435112

Sudhakar Kale - San Jose CA
Amit Chowdhary - Sunnyvale CA
Phani Saripella - Santa Clara CA
Naresh K. Sehgal - Santa Clara CA
Rajesh Gupta - Santa Clara CA

Intel Corporation - Santa Clara CA

G06F 1750

716 8, 716 2, 716 3

In some embodiments, a computer-aided design system comprises a functional regularity extraction component, a structural regularity extraction component and a floorplanning component. The functional regularity extraction component provides a method to extract regularity for circuits (and in particular datapath circuits) based on the functional characteristics of a logic design. Some embodiments of the functional regularity extraction component automatically generate a set of templates to cover a circuit. A template is a representation of a subcircuit with at least two instances in the circuit. The templates generated by the functional regularity extraction component are used by a structural regularity extraction component. The structural regularity extraction component provides a method to extract regularity for circuits (and in particular datapath circuits) based on the structural characteristics of a logic design. Some embodiments of the structural regularity extraction component automatically generate a set of vectors for the logic design.

7054191, May 30, 2006

Jun 3, 2004

10/860194

Rajesh Narendra Gupta - San Jose CA, US
Scott Robins - San Jose CA, US

T-Ram, Inc. - San Jose CA

G11C 11/39
G11C 11/34

365180, 365175, 36518901

A first and a second set of memory cells are connected to the same first word line and second word line. At the commencement of data writing, the first word line is set up. The first set of memory cells is read and temporarily stored into a buffer. At about the same time, the bit lines of the second set of memory cells is set up. After completion of reading of the first set of memory cells, the bit lines of this set of memory cells are set up (while the setting up of the bit lines of the second set of memory cells continues). After the bit lines of both sets of memory cells are set up, the second word line is pulsed. At this time, written into both sets of memory cells begins, which comprises data previously read from the first set of memory cells and new data to be written into the second set of memory cells. It is found that this method reduces the overall write time.

7316941, Jan 8, 2008

Jul 26, 2005

11/190242

Rajesh Gupta - Mountain View CA, US

T-RAM Semiconductor, Inc. - Milpitas CA

H01L 21/332

438133, 257E2135

In one embodiment, a thyristor device may be formed in series relationship with a MOSFET. Alternating regions of opposite conductivity type may be formed in semiconductor material for defining source, body and drain regions for the MOSFET device, and in series relationship to the thyristor. A primary dopant for a commonly-shared cathode/anode-emitter and drain/source region may have a concentration that is at least one order of magnitude greater than that of any background dopant therein. In a particular embodiment, the thyristor device and the MOSFET in series relationship therewith collectively define part of a thyristor-based memory.

7337418, Feb 26, 2008

Jul 14, 2003

10/621253

Sudhakar Kale - San Jose CA, US
Amit Chowdhary - Sunnyvale CA, US
Phani Saripella - Santa Clara CA, US
Naresh K. Sehgal - Santa Clara CA, US
Rajesh Gupta - Santa Clara CA, US

Intel Corporation - Santa Clara CA

G06F 17/50
G06F 9/45

716 5, 716 1, 716 10, 716 16, 716 17

In some embodiments, a computer-aided design system comprises a functional regularity extraction component, a structural regularity extraction component and a floorplanning component. The structural regularity extraction component provides a method to extract regularity for circuits (and in particular datapath circuits) based on the structural characteristics of a logic design. Some embodiments of the structural regularity extraction component automatically generate a set of vectors for the logic design. A vector is a group of template instances that are identical in function and in structure. The vectors generated by the structural regularity extraction component are used by a floorplanning component. The floorplanning component provides a method of generating a circuit layout from the set of vectors. In some embodiments, each vectors corresponds to a row in the circuit layout.

7554130, Jun 30, 2009

Feb 23, 2006

11/361869

Scott Robins - San Jose CA, US
Kevin J. Yang - Santa Clara CA, US
Rajesh N. Gupta - Mountain View CA, US

T-RAM Semiconductor, Inc. - Milpitas CA

H01L 29/74

257107, 257115

An integrated circuit having memory, including thyristor-based memory cells, is described, where each of the thyristor-based memory cells includes a thyristor-based storage element and an access transistor. Where the thyristor-based storage element includes an anode region and a cathode region, a pair of the thyristor-based memory cells are commonly coupled via a bitline associated with the access transistor or via a reference voltage line coupled to the anode region. Bitline or anode regions are separated from one another by an isolation region. In another configuration, a bitline region has a locally implant-damaged region to inhibit charge transfer between the pair. In yet another configuration, a storage node contact or contacts respectively can extend over or are coupled to a storage node line extending over an isolation region. In this latter configuration, a source/drain region and the cathode region are separated from one another by an isolation region.

8224943, Jul 17, 2012

Mar 28, 2008

12/058593

Matt Ocko - Palo Alto CA, US
George Tuma - Scotts Valley CA, US
Manish Kalia - Sunnyvale CA, US
Sandeep Sukhija - Milpitas CA, US
John Purrier - Seattle WA, US
Rajesh Gupta - Sunnyvale CA, US
Deepak Khajuria - Haryana, IN
Saumitra Das - Santa Clara CA, US

Ongoing Operations LLC - Hagerstown MD

G06F 15/173

709223

A service appliance is installed between production servers running service applications and service users. The production servers and their service applications provide services to the service users. In the event that a production server is unable to provide its service to users, the service appliance can transparently intervene to maintain service availability. To maintain transparency to service users and service applications, service users are located on a first network and production servers are located on a second network. The service appliance assumes the addresses of the service users on the second network and the addresses of the production servers on the first network. Thus, the service appliance obtains all network traffic sent between the production server and service users. While the service application is operating correctly, the service appliance forwards network traffic between the two networks using various network layers.

8324656, Dec 4, 2012

Jul 1, 2011

13/175676

Rajesh N. Gupta - Mountain View CA, US
Marc Laurent Tarabbia - Austin TX, US
Kevin J. Yang - Santa Clara CA, US

T-RAM Semiconductor, Inc. - Mountain View CA

H01L 29/74

257107, 257173, 257E27052, 257E27079, 257E29046

Embodiments of integrated circuits for mitigating against electrostatic coupling are described. In an embodiment, first gate dielectrics are respectively located over first active regions. First isolation regions are respectively located between the first active regions. Second gate dielectrics are respectively located over second active regions. Second isolation regions are respectively located between the second active regions. In an embodiment, the first active regions are approximately 20 to 80 percent shorter in height/thickness than the second active regions. In another embodiment, the first isolation regions extend above an uppermost surface of the first gate dielectrics while providing gaps between the first isolation regions and sidewalls of the first active regions for receipt of material used in formation of conductive lines. In yet another embodiment, active area stripes are narrower in width at p-base regions and n-base regions than at cathode regions and anode regions respectively thereof.

8504676, Aug 6, 2013

Jun 22, 2012

13/530986

Matt Ocko - Palo Alto CA, US
George Tuma - Scotts Valley CA, US
Sandeep Sukhija - Milpitas CA, US
John Purrier - Seattle WA, US
Rajesh Gupta - Sunnyvale CA, US
Deepak Khajuria - Haryana, IN
Saumitra Das - Santa Clara CA, US
Manish Kalia - Sunnyvale CA, US

Ongoing Operations LLC - Hagerstown MD

G06F 15/173

709223

A service appliance is installed between production servers running service applications and service users. The production servers and their service applications provide services to the service users. In the event that a production server is unable to provide its service to users, the service appliance can transparently intervene to maintain service availability. To maintain transparency to service users and service applications, service users are located on a first network and production servers are located on a second network. The service appliance assumes the addresses of the service users on the second network and the addresses of the production servers on the first network. Thus, the service appliance obtains all network traffic sent between the production server and service users. While the service application is operating correctly, the service appliance forwards network traffic between the two networks using various network layers.