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Rajiv Kapoor4921 69Th Avenue Ct W, Tacoma, WA 98467

Related to:
Devika Kapoor Lalloobhai Jivanbhai

Rajiv Kapoor Phones & Addresses

4921 69Th Avenue Ct W, University Pl, WA 98467    360-9513880   

University Place, WA   

Seatac, WA   

Houston, TX   

4921 69Th Avenue Ct W, University Place, WA 98467    360-7053412   

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Position: Handlers, Equipment Cleaners, Helpers, and Laborers Occupations

Education

Degree: High school graduate or higher
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Rajiv Kapoor Photo 35

Product Manager At Cisco

Location:
316 Bricknell Dr, Coppell, TX 75019
Industry:
Information Technology And Services
Work:
Lighthouse Ediscovery
Director of Product Marketing Microsoft Jul 2003 - Dec 2006
Product Marketing Management Cisco Jul 2003 - Dec 2006
Product Manager at Cisco
Education:
University College Dublin 2003 - 2004
University of Mumbai
Bachelors, Economics University College Dublin
Master of Business Administration, Masters, Marketing
Skills:
Product Management, Strategic Partnerships, Strategy, Management, Business Strategy, Go To Market Strategy, Product Marketing, Marketing, Leadership, Enterprise Software, Business Development, Software Product Management, Strategic Planning, Marketing Strategy, Brand Management, Digital Marketing, Advertising, Solution Selling
Interests:
Human Rights
Science and Technology
Arts and Culture
Politics
Rajiv Kapoor Photo 36

Rajiv Kapoor

Location:
University Place, WA
Industry:
Computer Hardware
Work:

Sw
Rajiv Kapoor Photo 37

Rajiv Kapoor

Location:
Seattle, WA
Industry:
Computer Software
Rajiv Kapoor Photo 38

Rajiv Kapoor

Rajiv Kapoor Photo 39

Rajiv Kapoor

Publications & IP owners

Wikipedia

Rajiv Kapoor Photo 41

Rajiv Kapoor

Rajiv Kapoor (born 25 August 1962) is an Indian film actor, producer, director and a member of the famous Kapoor Family. ...

Us Patents

Method And Apparatus For Performing Logical Compare Operations

US Patent:
7958181, Jun 7, 2011
Filed:
Sep 21, 2006
Appl. No.:
11/525706
Inventors:
Rajiv Kapoor - University Place WA, US
Ronen Zohar - Sunnyvale CA, US
Mark Buxton - Chandler AZ, US
Zeev Sperber - Zichron Yaakov, IL
Koby Gottlieb - Kiryat Tivon, IL
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 7/50
US Classification:
708671, 3401462
Abstract:
A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first data and a second data. The processor performs logical comparisons on the first and second data. The logical comparisons may be performed on each bit of the first and second data, or may be performed only on certain bits. For at least one embodiment, at least the first data includes packed data elements, and the logical comparisons are performed on the most significant bits of the packed data elements. The logical comparisons may include comparison of the same respective bits of the first and second data, and also includes logical comparisons of bits of the first data with the complement of the corresponding bits of the second data. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting one or more flags, which in turn may be utilized by a branching unit.

Method And Apparatus For Performing Logical Compare Operations

US Patent:
8380780, Feb 19, 2013
Filed:
Apr 8, 2011
Appl. No.:
13/082726
Inventors:
Rajiv Kapoor - University Place WA, US
Ronen Zohar - Sunnyvale CA, US
Mark Buxton - Chandler AZ, US
Zeev Sperber - Zichron Yaakov, IL
Koby Gottlieb - Kiryat Tivon, IL
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 7/50
US Classification:
708671, 708490
Abstract:
A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first data and a second data. The processor performs logical comparisons on the first and second data. The logical comparisons may be performed on each bit of the first and second data, or may be performed only on certain bits. For at least one embodiment, at least the first data includes packed data elements, and the logical comparisons are performed on the most significant bits of the packed data elements. The logical comparisons may include comparison of the same respective bits of the first and second data, and also includes logical comparisons of bits of the first data with the complement of the corresponding bits of the second data. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting one or more flags, which in turn may be utilized by a branching unit.

Method And Apparatus For Performing Logical Compare Operation

US Patent:
8606841, Dec 10, 2013
Filed:
Oct 19, 2012
Appl. No.:
13/656634
Inventors:
Rajiv Kapoor - University Place WA, US
Ronen Zohar - Sunnyvale CA, US
Mark J. Buxton - Chandler AZ, US
Zeev Sperber - Zichron Yaakov, IL
Koby Gottlieb - Kiryat Tivon, IL
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 7/50
US Classification:
708671, 708490
Abstract:
A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.

Method And Apparatus For Performing Logical Compare Operation

US Patent:
2013004, Feb 21, 2013
Filed:
Oct 19, 2012
Appl. No.:
13/656636
Inventors:
Rajiv Kapoor - University Place WA, US
Ronen Zohar - Sunnyvale CA, US
Mark Buxton - Chandler AZ, US
Zeev Sperber - Zichron Yaakov, IL
Koby Gottlieb - Kiryat Tivon, IL
International Classification:
G06F 9/30
US Classification:
712208, 712E09028
Abstract:
A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.

Method And Apparatus For Performing Logical Compare Operations

US Patent:
2013016, Jun 27, 2013
Filed:
Feb 8, 2013
Appl. No.:
13/763596
Inventors:
Rajiv Kapoor - University Place WA, US
Ronen Zohar - Sunnyvale CA, US
Mark Buxton - Chandler AZ, US
Zeev Sperber - Zichron Yaakov, IL
Koby Gottlieb - Kiryat Tivon, IL
International Classification:
G06F 9/30
US Classification:
712208
Abstract:
A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.

Method And Apparatus For Performing Logical Compare Operations

US Patent:
2013016, Jun 27, 2013
Filed:
Feb 8, 2013
Appl. No.:
13/763598
Inventors:
Rajiv Kapoor - University Place WA, US
Ronen Zohar - Sunnyvale CA, US
Mark Buxton - Chandler AZ, US
Zeev Sperber - Zichron Yaakov, IL
Koby Gottlieb - Kiryat Tivon, IL
International Classification:
G06F 9/30
US Classification:
712208
Abstract:
A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.

Method And Apparatus For Performing Logical Compare Operations

US Patent:
2013022, Aug 29, 2013
Filed:
Mar 15, 2013
Appl. No.:
13/843236
Inventors:
Rajiv Kapoor - University Place WA, US
Ronen Zohar - Sunnyvale CA, US
Mark J. Buxton - Chandler AZ, US
Zeev Sperber - Zichron Yaakov, IL
Koby Gottlieb - Kiryat Tivon, IL
International Classification:
G06F 9/30
US Classification:
712223
Abstract:
A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.

Possible Relatives

Deepak Kapoor  Devendra K Kapoor  Dinesh Kapoor  Divya Kapoor  Abhishek Kapoor  Gopal K Kapoor  Harish C Kapoor  Rajiv Singh  Rajiv Prasad  Rajiv P Das 

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