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Randy L Allmon, 674 Bridle Ridge Dr, North Grafton, MA 01536

Known as:
Randy Lee Allmon Randy Almon Allmon Randy
Related to:
Debra Williams Bennett 42

Randy Allmon Phones & Addresses

4 Bridle Ridge Dr, North Grafton, MA 01536    508-8392593   

296 Boylston St, Shrewsbury, MA 01545   

4 Patrick Rd, Hopedale, MA 01747    508-4788200   

10785 Blaney Ave, Cupertino, CA 95014    408-9618273   

Steubenville, OH   

Milford, MA   

Berkeley, CA   

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Randy L Allmon

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Work

Company: Intel corporation Position: Technology engineer

Skills

Soc • Vlsi • Semiconductors • Verilog • Asic • Engineering Management • Computer Architecture • Ic • Circuit Design • Microprocessors • Hardware Architecture • Integrated Circuit Design • Logic Design • Debugging • Static Timing Analysis • Systemverilog • Dft • Physical Design • Cmos • Microarchitecture • Simulations • Low Power Design • Timing Closure • Application Specific Integrated Circuits • Integrated Circuits • System on A Chip • Very Large Scale Integration • Processors • Rtl Design • Analog Circuit Design • Intel • Primetime • Rtl Coding

Industries

Computer Hardware
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Randy Allmon resumes & CV records

Resumes

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Randy Allmon

Location:
4 Bridle Ridge Dr, North Grafton, MA 01536
Industry:
Computer Hardware
Work:
Intel Corporation
Technology Engineer
Skills:
Soc, Vlsi, Semiconductors, Verilog, Asic, Engineering Management, Computer Architecture, Ic, Circuit Design, Microprocessors, Hardware Architecture, Integrated Circuit Design, Logic Design, Debugging, Static Timing Analysis, Systemverilog, Dft, Physical Design, Cmos, Microarchitecture, Simulations, Low Power Design, Timing Closure, Application Specific Integrated Circuits, Integrated Circuits, System on A Chip, Very Large Scale Integration, Processors, Rtl Design, Analog Circuit Design, Intel, Primetime, Rtl Coding

Publications & IP owners

Us Patents

Universal Cmos Single Input, Low Swing Sense Amplifier Without Reference Voltage

US Patent:
6414520, Jul 2, 2002
Filed:
Feb 1, 1999
Appl. No.:
09/241496
Inventors:
Robert J. Dupcak - Framingham MA
Randy L. Allmon - Hopedale MA
Mark D. Matson - Acton MA
Assignee:
Compaq Information Technologies Group, L.P. - Houston TX
International Classification:
G01R 1900
US Classification:
327 52, 327 57, 365205, 365208
Abstract:
A sense amplifier for sensing an input voltage level of a data signal. Such a sense amplifier pre-charges, and subsequently discharges, a pair of nodes through a respective pair of discharge paths. Each of those discharge paths is capable of performing the discharge operation at a rate that is related to either a system voltage supply or an input logic level of the data signal. Because the discharge path that is associated with the data signal includes a greater amount of conductance, it can perform the discharge operation at a faster rate, even where the input logic level does not exceed the voltage of the system voltage supply. A determination is made as to which of the discharge is the faster and, responsively, a rail-to-rail output signal having the same polarity as the data signal, is generated.

Universal Cmos Single Input, Low Swing Sense Amplifier Without Reference Voltage

US Patent:
6653869, Nov 25, 2003
Filed:
Feb 15, 2002
Appl. No.:
10/077194
Inventors:
Robert J. Dupcak - Framingham MA
Randy L. Allmon - Hopedale MA
Mark D. Matson - Acton MA
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G01R 1900
US Classification:
327 52, 327 57, 365207
Abstract:
A sense amplifier is provided for sensing an input voltage level of a data signal. Such a sense amplifier pre-charges, and subsequently discharges, a pair of nodes through a respective pair of discharge paths. Each of those discharge paths is capable of performing the discharge operation at a rate that is related to either a system voltage supply or an input logic level of the data signal. Because the discharge path that is associated with the data signal includes a greater amount of conductance, it can perform the discharge operation at a faster rate, even where the input logic level does not exceed the voltage of the system voltage supply. A determination is made as to which of the discharge is the faster and, responsively, a rail-to-rail output signal having the same polarity as the data signal, is generated. The input data signal is conveyed to the sense amplifier by a single wire. Also, the sense amplifier does not require a specialized reference voltage for proper operation.

Scan Friendly Domino Exit And Domino Entry Sequential Circuits

US Patent:
7227384, Jun 5, 2007
Filed:
Aug 11, 2005
Appl. No.:
11/201559
Inventors:
Mondira Pant - Westborough MA, US
Paul Gronowski - Northborough MA, US
Randy Allmon - North Grafton MA, US
Manjunath Bhat - Sunnyvale CA, US
David Lin - Westborough MA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03K 19/20
US Classification:
326112, 326 93
Abstract:
A circuit for converting received domino logic signals to a static output signal includes a pair of logic gates having inputs and outputs that are cross-coupled and responsive to a domino logic input signal and a clock signal to latch the input signal during an evaluation phase defined by the clock signal. A static output is based on the latched value. One of the logic gates is tri-stateable to establish a value at the static output during a scan mode. A circuit for converting received static logic signals into domino logic signals includes a latch responsive to a clock signal to latch the value of a data signal at a predefined clock transition. A conversion circuit produces a domino logic output signal in response to the clock signal and the latched value of the data signal. A latch component is tri-stateable to establish a value at the output.

Soft Error Reduction Circuit And Method

US Patent:
8278692, Oct 2, 2012
Filed:
Oct 22, 2009
Appl. No.:
12/589331
Inventors:
Vinod J. Ambrose - Northborough MA, US
Jeffrey D. Pickholtz - Marlborough MA, US
Randy L. Allmon - North Grafton MA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 29/78
US Classification:
257288, 257297, 257E29255
Abstract:
In some embodiments, complementary charge-collecting diffusions (transistor diffusions, e. g. , drain or source areas) are disposed close to each other. In some embodiments, dummy (“off”) transistors are incorporated to bring complementary diffusions (diffusions of the same charge type and having complementary digital logic levels) closer to each other than otherwise might be possible and thus, to enhance common-mode charge collection for the complementary diffusion areas.

Differential Sense Amplifier With Reduced Hold Time

US Patent:
6201418, Mar 13, 2001
Filed:
Aug 13, 1998
Appl. No.:
9/132797
Inventors:
Randy Lee Allmon - Hopedale MA
Assignee:
Compaq Computer Corporation - Houston TX
International Classification:
G01R 1900
US Classification:
327 52
Abstract:
A sense amplifier includes cross-coupled n-transistors that provide, from a predetermined time during one sample period to the start of the next precharge period, a path from a discharging internal node to the low supply voltage VSS. The n-transistors provide a discharge path from the time the internal node falls sufficiently below a precharge voltage to cause the transistors to operate differentially, until the time the node is again precharged, regardless of changes in the state of the input signals. The gate voltages of the cross-coupled transistors are controlled by the internal nodes, and the transistors participate in a positive feedback loop that drives the non-discharging internal node to a high supply voltage VDD through a cross-coupled p-transistor that is controlled by the discharging node. For a sense amplifier that precharges the pre-output nodes low, cross-coupled p-transistors similarly provide a path to VDD to charge the pre-output nodes from a point in one sample period to the start of the next precharge period, regardless of changes in the state of the input signals.

Leading One/Zero Bit Detector For Floating Point Operation

US Patent:
5317527, May 31, 1994
Filed:
Feb 10, 1993
Appl. No.:
8/016054
Inventors:
Sharon M. Britton - Westboro MA
Randy Allmon - Hopedale MA
Sridhar Samudrala - Westboro MA
Assignee:
Digital Equipment Corporation - Maynard MA
International Classification:
G06F 700
G06F 738
US Classification:
36471504
Abstract:
A circuit is provided for using the input operands of a floating point addition or subtraction operation to detect the leading one or zero bit position in parallel with the arithmetic operation. This allows the alignment to be performed on the available result in the next cycle of the floating point operation and results in a significant performance advantage. The leading I/O detection is decoupled from the adder that is computing the result in parallel, eliminating the need for special circuitry to compute a carry-dependent adjustment signal. The single-bit fraction overflow that can result from leading I/O misprediction is corrected with existing circuitry during a later stage of computation.

Latch With Redundancy And Circuitry To Protect Against A Soft Error

US Patent:
2017009, Mar 30, 2017
Filed:
Sep 25, 2015
Appl. No.:
14/866469
Inventors:
BALKARAN GILL - Cornelius OR, US
NORBERT R. SEIFERT - Beaverton OR, US
RANDY L. ALLMON - North Grafton MA, US
International Classification:
H03K 3/356
Abstract:
An apparatus is described having a latch circuit. The latch circuit includes redundant data inputs, redundant data outputs, redundant clock inputs and circuitry to self-correct a soft-error.

Variable Precision Floating Point Multiply-Add Circuit

US Patent:
2014018, Jul 3, 2014
Filed:
Dec 28, 2012
Appl. No.:
13/730390
Inventors:
Himanshu KAUL - Portland OR, US
Mark A. ANDERS - Hillsboro OR, US
Sanu K. MATHEW - Hillsboro OR, US
Ram K. KRISHNAMURTHY - Portland OR, US
William C. HASENPLAUGH - Cambridge MA, US
Randy L. ALLMON - North Grafton MA, US
Jonathan ENOCH - Worcester MA, US
International Classification:
G06F 17/10
US Classification:
708501
Abstract:
Embodiments of the present invention may provide methods and circuits for energy efficient floating point multiply and/or add operations. A variable precision floating point circuit may determine the certainty of the result of a multiply-add floating point calculation in parallel with the floating-point calculation. The variable precision floating point circuit may use the certainty of the inputs in combination with information from the computation, such as, binary digits that cancel, normalization shifts, and rounding, to perform a calculation of the certainty of the result. A floating point multiplication circuit may determine whether a lowest portion of a multiplication result could affect the final result and may induce a replay of the multiplication operation when it is determined that the result could affect the final result.

Possible Relatives

Cynthia Allmon  David L Allmon  Daniel M Allmon  Dustin P Allmon  Evelyn M Allmon  Frances F Allmon  Gregory L Allmon  Randy Johnson  Randy J Stamps  Randy L Johnston 

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