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Randy Wayne Cotton, 6317132 Ardisia Dr, Pflugerville, TX 78660

Randy Cotton Phones & Addresses

17132 Ardisia Dr, Pflugerville, TX 78660    512-2522307   

Austin, TX   

Travis, TX   

17132 Ardisia Dr, Pflugerville, TX 78660   

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Randy Cotton resumes & CV records

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Its Operations

Location:
Pflugerville, TX
Industry:
Information Services
Work:
State of Ohio
Its Operations
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Randy Cotton

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Randy Cotton

Publications & IP owners

Us Patents

Dual Metal Silicide Scheme Using A Dual Spacer Process

US Patent:
7544575, Jun 9, 2009
Filed:
Jan 19, 2006
Appl. No.:
11/337036
Inventors:
Olubunmi O. Adetutu - Austin TX, US
Dharmesh Jawarani - Round Rock TX, US
Randy W. Cotton - Pflugerville TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L 21/336
US Classification:
438299, 438592, 438664, 257E21438
Abstract:
A semiconductor process and apparatus provide a polysilicon structure () and source/drain regions () formed adjacent thereto in which a dual silicide scheme is used to form first silicide regions in the polysilicon, source and drain regions () using a first metal (e. g. , cobalt). After forming sidewall spacers (), a second metal (e. g. , nickel) is used to form second silicide regions in the polysilicon, source and drain regions () to reduce encroachment by the second silicide in the source/drain () and to reduce resistance in the polysilicon structure caused by agglomeration and voiding from the first silicide ().

Method Of Forming A Semiconductor Device Having A Dielectric Layer With High Dielectric Constant

US Patent:
2006006, Mar 23, 2006
Filed:
Sep 22, 2004
Appl. No.:
10/946938
Inventors:
Dina Triyoso - Austin TX, US
Olubunmi Adetutu - Austin TX, US
Randy Cotton - Pflugerville TX, US
International Classification:
H01L 21/336
US Classification:
438287000
Abstract:
A method for forming a semiconductor device () creates a dielectric layer () with high dielectric constant. An interfacial layer () is formed over a semiconductor substrate (). A dielectric layer () is formed over the interfacial layer, wherein the dielectric layer has a high dielectric constant (K). The dielectric layer is thinned, such as by etching or chemical mechanical polishing, wherein a thickness of the thinned dielectric layer is less than a thickness of the dielectric layer prior to thinning. In one form, the method is used to form a transistor having a gate electrode layer formed over the thinned dielectric layer and source/drain diffusions () within the semiconductor substrate.

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