Resumes & CV records
Resumes
Physical Design And Timing Lead
Location:
6150 Iowa Dr, San Jose, CA 95123
Industry:
Consumer Electronics
Work:
Apple
- Cupertino, California since Jun 2013
Physical Design (Timing) Engineer Intel Corporation - San Francisco Bay Area May 2012 - May 2013
Design Engineer Intel Jun 2011 - May 2012
Design Engineer Purdue University Aug 2009 - Jun 2011
Graduate Student and Teaching Assistant IBM May 2010 - Jul 2010
Research Intern - 28nm SRAM Characterization IBM Mar 2009 - Aug 2009
Research intern IBM May 2008 - Jul 2008
Summer Intern Systems and Technology Engineering Group Cadence Design Systems May 2007 - Jul 2007
Summer Intern Xilinx Design Corporations May 2006 - Jul 2006
Summer Intern
Physical Design (Timing) Engineer Intel Corporation - San Francisco Bay Area May 2012 - May 2013
Design Engineer Intel Jun 2011 - May 2012
Design Engineer Purdue University Aug 2009 - Jun 2011
Graduate Student and Teaching Assistant IBM May 2010 - Jul 2010
Research Intern - 28nm SRAM Characterization IBM Mar 2009 - Aug 2009
Research intern IBM May 2008 - Jul 2008
Summer Intern Systems and Technology Engineering Group Cadence Design Systems May 2007 - Jul 2007
Summer Intern Xilinx Design Corporations May 2006 - Jul 2006
Summer Intern
Education:
Purdue University 2009 - 2011
Masters of Science in ECE, Nanoelectronics Indian Institute of Technology, Madras 2004 - 2009
Dual Degree ( Integrated Btech+Mtech in 5 years), Electrical Engineering PCVN
Masters of Science in ECE, Nanoelectronics Indian Institute of Technology, Madras 2004 - 2009
Dual Degree ( Integrated Btech+Mtech in 5 years), Electrical Engineering PCVN
Skills:
Asic, Vlsi, Simulations, Fpga, Circuit Design, Very Large Scale Integration, Static Timing Analysis, Algorithms, Physical Design, Ic, Testing, Semiconductors, Verilog, Application Specific Integrated Circuits, Microprocessors, Xilinx, Microelectronics, Dft, Field Programmable Gate Arrays
Chef
Work:
Hotel Amor
Chef
Chef
Ratan Singh
Ratan Singh
Ratan Lal Singh
Ratan Singh
Ratan Singh