BackgroundCheck.run
Search For

Reed L Adams Deceased5175 Oakdale Ct, Pleasanton, CA 94588

Reed Adams Phones & Addresses

5175 Oakdale Ct, Pleasanton, CA 94588    925-4629089   

Castro Valley, CA   

Vallejo, CA   

Alameda, CA   

Mentions for Reed L Adams

Reed Adams resumes & CV records

Resumes

Reed Adams Photo 34

Reed Adams

Reed Adams Photo 35

Reed Adams

Reed Adams Photo 36

Director - New Product Development At Volterra

Position:
Director - New Product Development at Volterra
Location:
San Francisco Bay Area
Industry:
Semiconductors
Work:
Volterra - Fremont, CA since Jan 2012
Director - New Product Development
Analog Devices Feb 2009 - Dec 2011
Fixed Power Design Manager
Analog Devices Jun 2006 - Dec 2008
Development Center Manager
Texas Instruments Nov 1995 - May 2006
Analog / Mixed-Signal Design Engineer
Texas Instruments Jun 1994 - Oct 1995
Process and Equipment Engineer
Education:
Duke University - The Fuqua School of Business 2007 - 2008
EMBA, Executive MBA Program
Southern Methodist University 1994 - 1997
MS, Electrical Engineering
Texas A&M University 1990 - 1994
BS, Electrical Engineering
Honor & Awards:
PATENT AWARDS • Current Mirror Circuit that Allows for Over-Voltage Stress Testing, US #7,439,796; October, 2008. • Current Limiting Circuit for High-Speed Low-Side Driver Outputs, US #7,071,740; July, 2006. • Clamping Circuit for High-Speed Low-Side Driver Outputs, US #6,956,425; October, 2005. • System for Oxide Stress Testing, US #6,864,702; March, 2005. • Single-Poly EEprom on a negatively biased substrate, US #6,815,757; November, 2004. • Internal Protection Circuit and Method for On-Chip Programmable Poly Fuses, US #6,469,884; October, 2002. • Variable Transconductance Current Mirror Circuit, US #6,255,887; July, 2001. OTHER AWARDS Nominated Senior Member Technical Staff at TI in 2005. Elected Member of Group Technical Staff at TI in 2000.

Publications & IP owners

Us Patents

Esd Protection Circuit For A Switching Power Converter

US Patent:
8345394, Jan 1, 2013
Filed:
Oct 5, 2009
Appl. No.:
12/573501
Inventors:
James W. Zhao - San Francisco CA, US
Reed W. Adams - Mountain View CA, US
Kenji Tomiyoshi - Mihama-Ku Chiba, JP
Bin Shao - Shanghai, CN
Atsushi Matamura - Tokyo, JP
Yogesh Sharma - Santa Clara CA, US
Todd Thomas - San Jose CA, US
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
H02H 9/00
US Classification:
361 56
Abstract:
An ESD protection circuit for a switching power converter which includes a high-side switching element connected between a supply voltage and the switching node, and a low-side switching element connected between the switching node and a common node. A current conduction path couples an ESD event that occurs on the switching node to an ESD sense node, and an ESD sensing circuit coupled to the sense node generates a trigger signal when an ESD event is sensed. A first logic gate keeps the high-side switching element off when the trigger signal indicates the sensing of an ESD event, and a second logic gate causes the low-side switching element to turn on when an ESD event is sensed such that the low-side switching element provides a conductive discharge path between the switching node and common node.

NOTICE: You may not use BackgroundCheck or the information it provides to make decisions about employment, credit, housing or any other purpose that would require Fair Credit Reporting Act (FCRA) compliance. BackgroundCheck is not a Consumer Reporting Agency (CRA) as defined by the FCRA and does not provide consumer reports.