Reynaldo C Javier5624 Saint Thomas Dr, Plano, TX 75094

2009007, Mar 19, 2009

Sep 14, 2007

11/855784

Reynaldo Corpuz Javier - Plano TX, US
Jayprakash V. Chipalkatti - Dallas TX, US
Alok K. Lohia - Dallas TX, US

H01L 23/02
H01L 21/00

257686, 438109, 257E2318

Packaged integrated circuits and methods to form a thermal stacked integrated circuit package are disclosed. A disclosed method comprises attaching a first integrated circuit to at least one of a plurality of pads of a substrate, mounting a second integrated circuit above the first integrated circuit, placing a heat conductor in thermal contact with a top surface of the second integrated circuit, and encapsulating the first and second integrated circuits while leaving a surface of the heat conductor exposed to dissipate heat.

2011024, Oct 13, 2011

Oct 12, 2010

12/902306

Reynaldo C. Javier - Plano TX, US
Sreenivasan K. Koduri - Allen TX, US

Texas Instruments Incorporated - Dallas TX

H01L 23/495

257676, 257E23031

A ball grid array device () based on a metallic leadframe () that has the footprint of a BGA package with terminals () in a full two-dimensional array, and combines the structure of a leadframe with the function of a substrate. At least one terminal () is at the center of the device bottom. The terminals and leads () are made of metal having a greater thickness at the terminals than at the leads. The terminals may have a solderable surface. A semiconductor chip () is attached to the leadframe surface opposite the terminals, extending across adjacent leads.

2007029, Dec 27, 2007

Jun 27, 2006

11/426591

Anthony L. Coyle - Plano TX, US
Reynaldo C. Javier - Richardson TX, US
Jeffrey G. Holloway - Plano TX, US

TEXAS INSTRUMENTS INCORPORATED - Dallas TX

H01L 29/00

257531

An electronic device has a semiconductor chip () with a surface and an electric circuit including terminals on the surface. The circuit has a first () and a second terminal () with a metallurgical composition for wire bonding. The chip has a conductive wire () above the chip surface, which has a length and a first and a second end; the first end is attached to the first terminal and the second end to the second terminal. The wire is shaped to form at least one sequence of a concave and a convex portion. The sequence may be configured to form a loop, or multiple wire loops resulting in a spiraling wire coil. The number, shape, and spatial sequence of the loops control the electrical inductance of the wire; the inductance is selected to fine-tune the high frequency characteristics of the circuit.

2017006, Mar 2, 2017

Sep 1, 2015

14/842535

- Dallas TX, US
ALOK KUMAR LOHIA - DALLAS TX, US
REYNALDO CORPUZ JAVIER - PLANO TX, US

H01L 23/10
H01L 23/00
H01L 23/057
H01L 21/54
H01L 21/48
H01L 23/08
H01L 21/52

A method of assembling a semi-hermetic semiconductor package includes bonding a semiconductor die having bond pads to a top side of a base region of a package substrate having vertical side walls that are hollow which define an inner open volume (gap) having an adhesive or thermoplastic material therein. There are a plurality of metal terminals providing top terminal contacts on the top side of the base region and bottom terminal contacts on a bottom side or below the base region. The bond pads are coupled to the top terminal contacts. A lid is placed which provides a top for the semiconductor package, where the lid extends to vertically oriented end protrusions so that the protrusions are positioned within the adhesive or thermoplastic material to secure the protrusions within the adhesive or thermoplastic material to provide a seal for the semiconductor package.

2016023, Aug 11, 2016

Apr 15, 2016

15/099864

- Dallas TX, US
Reynaldo Corpuz Javier - Plano TX, US
Andy Quang Tran - Grand Prairie TX, US

H01L 23/495
H01L 21/48
H01L 21/56
H01L 23/31

A semiconductor device comprising a stack of semiconductor chips. The semiconductor chips have an electrically active side and an opposite electrically inactive side. The active sides bordered by an edge having first lengths and the inactive sides bordered by a parallel edge having a second lengths smaller than the first lengths. A substrate has an assembly pad bordered by a linear edge having a third length equal to or smaller than the first lengths. The inactive chip side attached to the pad so that the edge of the first lengths are parallel to the edge of the third length. The active side of the attached chip forms an overhang over the pad, when the third length is smaller than the first lengths.

2016018, Jun 23, 2016

Dec 23, 2014

14/580836

- Dallas TX, US
Reynaldo Corpuz Javier - Plano TX, US
Andy Quang Tran - Grand Prairie TX, US

H01L 23/495
H01L 25/00
H01L 23/00
H01L 21/78
H01L 21/56

A semiconductor device () comprising a semiconductor chip () has an electrically active side () and an opposite electrically inactive side (); the active side bordered by an edge having a first length (), and the inactive side bordered by a parallel edge having a second length () smaller than the first length; a substrate has an assembly pad () bordered by a linear edge having a third length () equal to or smaller than the first length; the inactive chip side attached to the pad so that the edge of the first length is parallel to the edge of the third length; the active side of the attached chip forms an overhang over the pad, when the third length is smaller than the first length.

2016007, Mar 10, 2016

Sep 15, 2015

14/854651

- Dallas TX, US
Reynaldo Corpuz Javier - Plano TX, US
Andy Quang Tran - Grand Prairie TX, US

H01L 23/495
H01L 23/29
H01L 21/78
H01L 23/31
H01L 21/48
H01L 21/56

A semiconductor device has a leadframe with a pad and a row of elongated leads with a solderable surfaces in a common plane; a package encapsulating the leadframe with an assembled semiconductor device, leaving the common-plane lead surfaces un-encapsulated and coplanar with the package material between adjacent leads, the row of aligned leads positioned along a package edge; and grooves in the package material cut in the common-plane surface, the grooves extend along a portion of each lead length, have a width and a depth about twice the width, and expose solderable lead surfaces.

2016000, Jan 7, 2016

Sep 15, 2015

14/854886

- Dallas TX, US
Reynaldo Corpuz Javier - Plano TX, US
Alok Kumar Lohia - Dallas TX, US

H01L 23/00
H01L 21/78
H01L 21/56
H01L 21/48

A method for fabricating a semiconductor device package provides a metallic leadframes with a plurality of device sites. Each site including a pad and a plurality of leads with solderable surfaces. At least one set of leads are aligned in a row and are connected by rails to respective leads of an adjacent site. The leads and rails of the row having a surface in a common plane. The strip with the assembled sites and connecting rails are encapsulated in a packaging material, leaving the common-plane lead and rail surfaces un-encapsulated. Trenches are cut between adjacent sites by removing packaging material until reaching the rails. Thus, creating sidewalls of device packages connected by rails. Device packages are singulated from the strip by severing the connecting rails between adjacent sites in approximate halves, leaving a respective rail half as a straight protrusion attached to each lead. The protrusions are bent at an angle away from the common plane towards the package sidewall.