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Rejitha Nair3220 Tearose Dr, Richardson, TX 75082

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3220 Tearose Dr, Richardson, TX 75082   

Mesquite, TX   

Dallas, TX   

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Rejitha Nair

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United States

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Us Patents

Hardware Implementation Of A Galois Field Multiplier

US Patent:
2011006, Mar 10, 2011
Filed:
Sep 3, 2010
Appl. No.:
12/875732
Inventors:
Shriram D. Moharil - Allen TX, US
Rejitha Nair - Richardson TX, US
Assignee:
TEXAS INSTRUMENTS INCORPORATED - Dallas TX
International Classification:
G06F 7/60
US Classification:
708230, 708492
Abstract:
An embodiment of the invention provides a method of operating a Galois field multiplier in a processor. An n bit multiplier and an n bit multiplicand are received during a first group of one or more clock cycles. An (2n−1) bit product is calculated based on the n bit multiplicand and the n bit multiplier. The (2n−1) bit product is stored in a first memory element during the first group of one or more clock cycles. An n bit polynomial value is received during a second group of one or more clock cycles. During the second group of one or more clock cycles, the (2n−1) bit product is divided by the n bit polynomial value producing an n bit result. The n bit result is stored in a second memory element during the second group of one or more clock cycles.

Integrated Circuit With State Machine For Pre-Boot Self-Tests

US Patent:
2021020, Jul 8, 2021
Filed:
Dec 30, 2020
Appl. No.:
17/138684
Inventors:
- Dallas TX, US
Rejitha NAIR - Southlake TX, US
International Classification:
G06F 11/36
G01R 31/317
Abstract:
An integrated circuit includes a processor core configured to perform boot operations; and a microcontroller coupled to a processor core. The microcontroller includes: a set of microcontroller components; and a state machine coupled to the set of microcontroller components. The state machine is configured to perform self-test operations on the set of microcontroller components before the boot operations.

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