Xin Wu, 6514648 Birch St, San Leandro, CA 94579

6364956, Apr 2, 2002

Jan 26, 1999

09/237502

Youqi Wang - Atherton CA
Xin Di Wu - San Jose CA

Symyx Technologies, Inc. - Santa Clara CA

C23C 1600

118726, 118723 EB, 392388, 21912115, 20429801

An apparatus for simultaneously depositing gradients components of two or more target materials onto a substrate is disclosed. The apparatus comprises a first target material source that directs a first target material towards the substrate and a second target material source that directs a second material towards the substrate. The apparatus further comprises a gradient shutter system that blocks a first predetermined amount of the first target material and a second predetermined amount of the second target material directed towards the substrate in order to generate gradients of the first and second target materials on the substrate. The gradients of the first and second target materials being simultaneously deposited onto the substrate to form a homogenous resulting material. A method for simultaneously depositing gradients of two or more target material onto a substrate is also disclosed.

6376131, Apr 23, 2002

Apr 4, 2000

09/542127

Jae Cho - Sunnyvale CA
Zhi-Min Ling - Cupertino CA
Xin X. Wu - Fremont CA

Xilinx, Inc. - San Jose CA

G03F 900

430 5

A reticle that is modified to prevent bridging of the masking material (e. g. , chrome) between portions of the lithographic mask pattern during an integrated circuit fabrication process. According to a first aspect, the modification involves electrically connecting the various portions of the lithographic mask pattern that balance charges generated in the portions during fabrication processes. In one embodiment, sub-resolution wires that extend between the lithographic mask pattern portions facilitate electrical conduction between the mask pattern portions, thereby equalizing dissimilar charges. In another embodiment, a transparent conductive film is formed over the lithographic mask pattern to facilitate conduction. In accordance with a second aspect, the modification involves separating the various portions of the lithographic mask pattern into relatively small segments by providing sub-resolution gaps between the various portions, thereby minimizing the amount of charge that is generated on each portion.

6569584, May 27, 2003

Jun 29, 2001

09/895538

Jonathan J. Ho - Fremont CA
Xin X. Wu - Fremont CA

Xilinx, Inc. - San Jose CA

G03F 900

430 5

A reticle (mask) that is modified to prevent bridging of the masking material (e. g. , chrome) between long mask lines of a lithographic mask pattern during an integrated circuit fabrication process. A dummy mask pattern is provided on the reticle adjacent to long mask lines that causes the large charge collected on the long mask line to be distributed along its length, thereby minimizing voltage potentials across a gap separating the long mask line from an adjacent mask line.

6632285, Oct 14, 2003

Jul 30, 2001

09/919168

Youqi Wang - Atherton CA
Xin Di Wu - San Jose CA

Symyx Technologies, Inc. - Santa Clara CA

C23C 1600

118726, 118723 EB

An apparatus for simultaneously depositing gradients components of two or more target materials onto a substrate is disclosed. The apparatus comprises a first target material source that directs a first target material towards the substrate and a second target material source that directs a second material towards the substrate. The apparatus further comprises a gradient shutter system that blocks a first predetermined amount of the first target material and a second predetermined amount of the second target material directed towards the substrate in order to generate gradients of the first and second target materials on the substrate. The gradients of the first and second target materials being simultaneously deposited onto the substrate to form a homogenous resulting material. A method for simultaneously depositing gradients of two or more target material onto a substrate is also disclosed.

6645802, Nov 11, 2003

Jun 8, 2001

09/877690

Shahin Toutounchi - Pleasanton CA
Michael J. Hart - Palo Alto CA
Xin X. Wu - Fremont CA
Daniel Gitlin - Palo Alto CA

Xilinx, Inc. - San Jose CA

H01L 218234

438237, 438983, 438328

An ESD protection circuit includes a bipolar transistor, a resistor, and a zener diode formed on and within a semiconductor substrate. The resistor extends between the base and emitter regions of the transistor so that voltage developed across the resistor can turn on the transistor. The zener diode is formed in series with the resistor and extends between the base and collector regions of the transistor. Thus configured, breakdown current through the zener diode, typically in response to an ESD event, turns on the transistor to provide a nondestructive discharge path for the ESD. The zener diode includes anode and cathode diffusions. The cathode diffusion extends down into the semiconductor substrate in a direction perpendicular to the substrate. The anode diffusion extends down through the cathode diffusion into the semiconductor substrate. The anode diffusion extends down further than the cathode diffusion so that the zener diode is arranged vertically with respect to the substrate.

6868537, Mar 15, 2005

Feb 25, 2002

10/082991

Jonathan J. Ho - Fremont CA, US
Xin X. Wu - Fremont CA, US
Zicheng Gary Ling - San Jose CA, US
Jan L. de Jong - Cupertino CA, US

Xilinx, Inc. - San Jose CA

G06F017/50

716 19, 716 20, 716 21

For IC devices that have repeating structures, a method of generating a database for making a mask layer starts with a hierarchical database describing at least one repeating element in the layer, a skeleton that surrounds the repeating elements, and instructions as to where to locate the repeating elements within the skeleton. This database is modified to generate a database that has optical proximity correction (OPC) for diffraction of light that will pass through the mask and expose photoresist on the IC layer. The optical-proximity corrected mask database is fractured by a mask house using instructions on how the modified data base will be divided to form repeating elements that are still identical after OPC, a mask skeleton that includes non-repeating elements, and instructions for placement of the repeating elements in the skeleton. Thus the resulting mask database is smaller than a mask database that includes all copies of repeating elements.

7064450, Jun 20, 2006

May 11, 2004

10/842756

Abu K. Eghan - San Jose CA, US
Richard C. Li - Cupertino CA, US
Xin X. Wu - Fremont CA, US

Xilinx, Inc. - San Jose CA

H01L 23/48

257786, 257 48, 257692, 257773, 257775, 257780

A pad pattern of a die includes first and second sets of elongated pads. The first set of elongated pads is interleaved with the second set of elongated pads. Each of the elongated pads has a bond pad area and a probe pad. Each bond pad area has a first constant width along a substantial portion thereof. Similarly, each probe pad area has a second constant width along a substantial portion thereof. The first constant width is greater than the second constant width. Each elongated pad in the first set has a first orientation. Similarly, each elongated pad in the second set has a second orientation, opposite the first orientation.

7235412, Jun 26, 2007

May 11, 2004

10/842770

Mohsen Hossein Mardi - Fremont CA, US
Jae Cho - Saratoga CA, US
Xin X. Wu - Fremont CA, US
Chih-Chung Wu - Hsinchu, TW
Shih-Liang Liang - Chung Li, TW
Sanjiv Stokes - Los Altos CA, US
Hassan K. Bazargan - San Jose CA, US

XILINX, Inc. - San Jose CA

H01L 21/66

438 14, 438 15, 438 18

A semiconductor component having test pads and a method and apparatus for testing the same is described. In an example, an un-bumped substrate is obtained having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. In another example, a substrate is fabricated having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. An insulating layer is formed over the plurality of test pads.